SiFive Launches New RISC-V AI IP with Scalar Vector and Matrix Compute

SiFive has recently unveiled its latest addition to the RISC-V AI portfolio with the introduction of the 2nd Generation Intelligence family. This new lineup includes five processor IPs specifically designed to enhance AI workloads across various computing environments, ranging from the far edge to the data center. Among the new cores are the X160 Gen 2 and X180 Gen 2, along with updated versions of the X280, X390, and XM processors.

For readers of eeNews Europe, this announcement underscores the growing maturity of RISC-V as an architecture for AI acceleration. It offers scalable computing solutions for developers working on a wide range of applications, including IoT devices and high-performance data center platforms. The availability of these new processor IPs also reflects a broader industry trend towards adopting open-standard instruction sets for advanced AI applications.

Enhancing the RISC-V AI Lineup

The X160 Gen 2 and X180 Gen 2 processors are specifically tailored for far-edge computing and IoT applications, where space and energy efficiency are critical factors. These cores enable advanced AI capabilities in embedded environments such as automotive systems, robotics, and industrial automation. On the other hand, the upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 processors cater to higher-performance markets, with the XM processor leveraging matrix acceleration to handle complex AI workloads.

Patrick Little, the CEO of SiFive, emphasized the pivotal role of AI in driving the evolution of the RISC-V ecosystem. He highlighted the strong market interest in the new X100 series, with two Tier 1 U.S. semiconductor companies already adopting these processors. The 2nd Generation Intelligence IP lineup builds upon this momentum by introducing new features and configurability to expedite customer designs and time to market.

Vector and Matrix Compute for AI

A key distinguishing feature of the new processor lineup is the incorporation of vector processing capabilities. By executing multiple data items simultaneously, vector engines reduce instruction overhead and power consumption compared to scalar-only CPUs. This efficiency allows AI models to run faster while consuming less energy and silicon area, which is crucial for edge AI devices. At the top end, the XM Gen 2 processor integrates a matrix engine that can be scaled for demanding AI and machine learning tasks.

SiFive places a strong emphasis on configurability across its portfolio, providing designers with a unified ISA that caters to diverse computing requirements. This flexibility enables developers to tailor their AI solutions to specific application needs while leveraging the efficiency of RISC-V architecture.

Accelerator Control Capabilities

Another notable feature of the X-Series IPs is their ability to function as Accelerator Control Units (ACUs). Through co-processor interfaces like SSCI and VCIX, these cores offer control and support functions for custom accelerators. This approach empowers customers to innovate at the platform level while streamlining software complexity, ultimately enhancing the overall performance and efficiency of AI-enabled systems.

Availability

SiFive has confirmed that all five 2nd Generation Intelligence products are currently available for licensing, with the first silicon expected to be available in Q2 of 2026. This expanded portfolio presents developers with a pathway to scalable and power-efficient RISC-V computing solutions for next-generation AI systems, spanning from the embedded edge to the data center.