Cadence tapes out UCIe IP at 64Gbps on TSMC N3P

Cadence recently announced the tapeout of its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution, capable of supporting data rates of up to 64 Gbps per lane on TSMC’s N3P process. This development underscores the growing interest in chiplet-based architectures as designers strive for increased bandwidth and tighter integration at advanced nodes. The momentum around UCIe IP is particularly relevant for European engineers working on multi-die integration for AI accelerators, high-performance computing, and data center platforms where bandwidth density and power efficiency are becoming crucial system-level considerations.

The UCIe IP from Cadence is designed to target higher bandwidth requirements at advanced nodes, aligning with the UCIe specification to facilitate scalable die-to-die interconnects at leading-edge process technologies. By leveraging TSMC’s N3P node, the solution aims to deliver enhanced performance-per-watt compared to previous implementations, although the ultimate system-level benefits will be influenced by packaging choices, integration strategies, and workload characteristics.

As part of a broader strategy to address power, performance, and area trade-offs associated with designs transitioning to 3nm-class nodes, Cadence emphasizes the importance of high-speed die-to-die links in the context of heterogeneous integration strategies replacing traditional monolithic scaling. The UCIe IP supports multiple protocols, including AXI, CXS, CHI-C2C, PCIe, and CXL, offering flexibility for integration into diverse chiplet-based systems, which could be advantageous for European designers working across varied ecosystems or aiming for platform reuse.

With a data rate of 64 Gbps per lane, the UCIe IP is positioned to meet the high aggregate bandwidth requirements of AI and HPC workloads, crucial for demanding applications in these domains. Cadence highlights the significance of advanced packaging technologies in achieving optimal bandwidth density figures, indicating that packaging approaches play a critical role in realizing the full potential of high-speed interconnect IP solutions.

Additionally, the UCIe IP features error correction, lane margining, and diagnostic support functionalities to enhance robustness during system bring-up and operation. Cadence emphasizes the self-calibrating capabilities of the IP, potentially reducing the need for firmware intervention during system initialization and thereby shortening development cycles. Arif Khan, vice president of marketing in the Silicon Solutions Group at Cadence, expressed pride in the release of the third-generation UCIe IP, stating, “Given the insatiable demand for throughput and efficiency driven by AI and HPC applications, we are proud to make our third-generation UCIe IP—achieving speeds of 64G—available.”