Cryo-CMOS multiplexing for quantum spin qubits

Researchers at VTT in Finland have developed a 64 channel on-chip multiplexer for quantum spin qubits.

The team developed on-chip interfaces for tunable electron and hole dual quantum dots with a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation to avoid heating up the spin qubits.

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This hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of quantum dot devices, enabling, for example, variability analysis and QD qubit geometry optimization for building large-scale silicon-based quantum computers.

The chip is built on a custom silicon on insulator (SOI) process with an all-silicon gate stack and 50nm gate width. This shows low noise at a relatively high temperature of 5.6K down to 300mK.

The cryogenic MUX is composed of a 6-to-64 decoder made of standard CMOS logic gates, and analog switches using a transmission gate design that features a pair of electron n- and hole p- MOSFETs. The MUX logic features a supply power line VDD, ground contact (GND), and the 6 address line voltages.

In March, VTT spin out SemiQon started shipping a 4-qubit quantum dot array from the first production run at its manufacturing facility in Espoo, Finland. T

“We are gradually moving towards the million qubit era and the contribution of hardware is becoming more and more essential,” says Dr. Himadri Majumdar, CEO and Co-founder of SemiQon. “Our solution builds on the technological development and know-how of semiconductors and benefits from existing infrastructure and industry. Utilizing such infrastructure effectively and efficiently has allowed us to accomplish one of our first goals within a short period of time. The challenge is getting to quantum supremacy in a sustainable, scalable, and affordable manner. These new chips are our first step in a long journey to making quantum dreams a reality.”