ZF and SiliconAuto unveil real-time IO chip for self-driving cars

A groundbreaking chip architecture tailored for high-performance computing in autonomous vehicles has been introduced by ZF and SiliconAuto. Unveiled at embedded world 2026 in Nuremberg, the companies showcased a real-time I/O interface chip coupled with a microcontroller, illustrating how sensor data for automated driving systems can be acquired and pre-processed directly in hardware.

This innovative design is specifically aimed at next-generation Advanced Driver Assistance Systems (ADAS) and automated driving platforms, offering enhanced efficiency and flexibility when compared to traditional monolithic SoC architectures. For automotive engineers and system designers keeping abreast of computational trends in the industry, this approach underscores a transition towards modular chiplet-based architectures and increased integration with AI inference engines.

Real-time sensor processing moves closer to the edge

The collaborative demonstration revolves around a newly developed ZF I/O interface chip that conducts real-time sensor data acquisition and pre-processing. This chip incorporates various automotive sensor interface IP blocks and processing capabilities, including low-latency camera image signal processing and on-chip radar signal processing.

Within the demonstration setup, the chip collaborates with SiliconAuto’s XMotiv M3 microcontroller, which serves as the system’s safety controller. Operating at 160 MHz, the controller manages tasks such as secure boot, power sequencing, clock management, and reset supervision.

A primary objective of the design is to alleviate the load on central compute processors. By managing sensor interfacing and initial processing locally, the interface chip reduces data transfers to DDR memory, enabling the primary high-performance SoC to concentrate on perception and driving algorithms. According to the companies, this architecture has the potential to decrease power consumption and enhance overall system efficiency.

A modular alternative to monolithic automotive SoCs

The architecture also aims to provide automotive OEMs with more flexibility in selecting their compute platforms. Instead of depending on a single large SoC, the new design connects to a preferred performance processor using standardized high-speed interfaces like PCIe or Ethernet.

This SoC-agnostic approach implies that processors lacking native automotive sensor interfaces — such as CSI-2, CAN, or LVDS — can be seamlessly integrated into the system. Consequently, automakers can pair the interface chip with various AI inference engines or compute solutions based on their performance requirements.

The platform is engineered to scale from entry-level ADAS applications to advanced automated driving systems approaching SAE Level 4 autonomy. Modular chiplets enable individual components to be upgraded without necessitating a complete redesign of the compute architecture.

Toward open automotive chiplet ecosystems

Looking forward, the companies are planning to endorse open die-to-die interconnect standards like UCIe, allowing the I/O component to evolve into a fully compliant chiplet. This would empower OEMs to independently choose compute, AI acceleration, and I/O components while retaining long-term design flexibility.

The initiative also aligns with broader European semiconductor objectives. It received support from Germany’s Federal Ministry for Education, Research and Space through the ZuSEKI-mobil program, which concentrates on secure and sustainable microelectronics development in Europe.

Besides enhancing flexibility, the companies argue that the modular chiplet strategy can prolong the lifespan of high-performance automotive compute platforms while curbing energy consumption — a critical consideration as vehicles integrate more sensors and AI processing capabilities.