Embedded AI accelerators with advanced debugging support in UDE 2026

As the deployment of embedded AI workloads transitions from research to production silicon, the demand for advanced development tools is on the rise. PLS has recently updated its Universal Debug Engine to cater to the unique challenges presented by highly parallel, data flow-based accelerators integrated into microcontrollers and SoCs.

For engineers and developers in the AI-enabled automotive and industrial sectors, the capability to analyze and validate accelerator behavior in real-time is becoming increasingly crucial. Having debug visibility at the system level is essential when integrating dedicated AI hardware and embedded AI accelerators alongside traditional CPU cores.

Enhanced Debugging for Data Flow Architectures

The latest release of UDE 2026 expands its debug, trace, and test functionalities to encompass specialized data flow-oriented algorithms commonly used in embedded AI applications. This update empowers developers to apply advanced analysis techniques to embedded AI accelerators based on data flow architectures.

Unlike traditional instruction-based processors, data flow architectures implement algorithms as interconnected mathematical building blocks arranged in a native data flow graph. This approach has the potential to offer increased efficiency in terms of silicon area and power consumption, making it a suitable choice for integration into embedded systems and SoCs targeting AI workloads.

However, analyzing graph-based execution models requires more than conventional debugger functions. To address this, PLS has enhanced UDE with dedicated features designed to analyze and debug the data flow graph of DFA.

Enhanced System-Level Visibility and Runtime Analysis

Within an embedded system, the DFA accelerator can be initiated and halted either independently or in synchronization with the host controller cores. In UDE, it is represented as an additional core within a run control group, facilitating synchronized debugging across the main cores and the accelerator.

This setup enables parallel debugging of the application software running on the main cores while monitoring the behavior of the accelerator. Through single-stepping, developers can delve into the data flow intricacies, verifying or modifying the configuration of individual base blocks.

The data flow graph is visually represented, such as in a tree or block diagram format, with various display options that developers can customize to suit their requirements. Additionally, import and export functions for DFA configurations are integrated into the tool.

For runtime analysis, a SystemC simulation model can capture DFA runtime data. A specialized software component decodes and presents this data in both textual and time-correlated graphical formats, aiding in comprehensive analysis and debugging.

These additional test and analysis capabilities are now accessible for the latest automotive microcontrollers implementing DFA, as well as for virtual prototyping utilizing the DFA simulation model, providing engineers with a comprehensive toolset for developing and optimizing embedded AI applications.