Eliyan Unveils Cutting-Edge 3nm Chiplet Interconnect Technology

Startup Eliyan has made waves in the tech industry by successfully shipping the first silicon of its groundbreaking chiplet interconnect solution. The Eliyan NuLink-2.0 PHY, manufactured using cutting-edge 3nm process technology, has achieved a remarkable 64Gbps/bump, setting a new standard for die-to-die PHY solutions in multi-die architectures, including compatibility with the emerging HBM4 memory devices.

While adhering to the UCIe standard, the NuLink-2.0 silicon demonstrator has showcased its capability to double the bandwidth for die-to-die connectivity in both standard and advanced packaging configurations. This versatility positions the NuLink-2.0 as a game-changer in the realm of chiplet interconnect technologies.

The NuLink-2.0 is not just a one-trick pony; it is a multi-mode PHY solution that also supports UMI (Universal Memory Interconnect), a proprietary technology that significantly enhances Die-to-Memory bandwidth efficiency. UMI leverages a dynamic bidirectional PHY, currently undergoing finalization of specifications with the Open Compute Project (OCP) as BoW 2.1, promising to revolutionize data transfer efficiency.

The NuLink-2.0 demo vehicle utilizes standard organic/laminate packaging with 5-2-5 and 8-2-8 stack ups, showcasing its remarkable area efficiency. The NuLink PHY's bump limitation allows it to fit snugly under 90um bump pitch in standard packaging and even under 45-55um bump pitches in advanced packaging, enabling impressive bandwidth capabilities.

With the potential to deliver up to 5Tbps/mm in standard packaging and up to 21Tbps/mm in advanced packaging, the NuLink-2.0 is a versatile solution that caters to a wide range of applications. Its die-to-die PHY, coupled with an adaptor/link layer controller IP, offers a comprehensive solution tailored for high-growth AI markets, including applications in HPC and edge computing.

According to Eliyan's founding CEO Ramin Farjadrad, "This milestone sets a new standard in Perf/TCO advantages for implementing a wide range of multi-die use cases. The performance, combined with low power consumption and packaging flexibility, opens up new possibilities for chiplet-based designs across various industries."