Huawei 1.4 nm Target Leans on Tau Scaling Law

Huawei has set out a 2031 target for high-end chips with transistor density equivalent to 14 Å, or 1.4 nm, processes, using a design principle it calls the Tau (τ) Scaling Law. The Huawei 1.4 nm claim is not a statement that China has solved leading-edge lithography. It is an attempt to move part of the scaling argument away from gate geometry and towards timing, interconnect and system-level efficiency.

In a conference announcement, Huawei said He Tingbo presented the approach at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai. The associated LogicFolding architecture is presented as a way to shorten critical-path wiring and reduce the resistive and capacitive load of signal propagation.

Huawei 1.4 nm target is about equivalent density

The distinction matters. Modern process-node labels are no longer literal descriptions of transistor dimensions, and Huawei is using equivalence language. It says high-end chips designed using the τ Scaling Law are expected by 2031 to reach transistor density equivalent to 14 Å processes.

Huawei also says it has designed and mass-produced 381 chips over the past six years using the approach, covering sectors including smartphones and AI computing. Kirin chips scheduled for autumn 2026 are due to be the first to adopt LogicFolding, while the longer-term promise is that delay reduction at device, circuit, chip and system level can produce more useful performance from constrained manufacturing options.

What the Huawei 1.4 nm roadmap does not prove

The comparison point is aggressive. TSMC describes A14 as its next cutting-edge logic process and says it is on track for volume production in 2028. Huawei’s target lands three years later and is framed around equivalent transistor density rather than a conventional foundry node.

The sanctions angle is unavoidable. US controls have limited China’s access to the most advanced lithography and other chipmaking technologies, forcing Chinese companies to explore routes through design, packaging and more complex DUV-based processing. That direction was already visible, as previously reported by eeNews Europe when Huawei pursued quad patterning for 5 nm chips.

Tau Scaling Law is therefore best read as a strategic workaround rather than a clean leap to the front of the process race. Shorter interconnects, lower latency and better data movement can matter a great deal, especially in AI accelerators and large compute systems. But power, heat, yield, design-tool support and software will decide whether the Huawei 1.4 nm roadmap becomes a competitive product path or remains a strong conference claim.