TSMC SoIC Roadmap Targets 2029 Chip Stacking

Advanced packaging is playing an increasingly crucial role in the performance scaling of AI and high-performance computing designs, with TSMC leading the way in pushing its 3D chip-stacking roadmap towards finer interconnect pitches and tighter integration. The updated TSMC SoIC roadmap, unveiled after the company’s 2026 North America Technology Symposium, outlines a progression from 6 µm pitches to 4.5 µm by 2029. This direction is significant as pitch scaling directly impacts the number of vertical interconnects that can be accommodated between chiplets.

At the same symposium, TSMC announced that A14-to-A14 SoIC is slated for production in 2029, offering 1.8x higher die-to-die I/O density compared to N2-on-N2 SoIC. Positioned as part of the 3DFabric advanced packaging family, alongside CoWoS and InFO, the technology is set to enhance performance and efficiency in chiplet integration.

SoIC, or System on Integrated Chips, is TSMC’s 3D stacking technology designed for heterogeneous chiplet integration. By moving towards face-to-face stacking, where active metal layers of two dies are aligned directly and connected using hybrid copper bonding, TSMC aims to reduce size, increase performance, and lower resistance, inductance, and capacitance. This shift marks a significant technical advancement in chiplet integration.

Broadcom has highlighted the benefits of face-to-face stacking, citing a substantial increase in signal density compared to face-to-back stacking. The practical advantages include higher bandwidth and lower latency between stacked dies. Despite the thermal and manufacturing challenges that come with this approach, the potential for improved performance is driving the industry towards embracing face-to-face chiplet stacking.

Fujitsu’s Monaka processor is set to be one of the early adopters of face-to-face chiplet stacking technology. Utilizing Broadcom’s 3.5D XDSiP platform, which combines 2.5D integration and 3D-IC stacking using face-to-face technology, the Monaka initiative aims to deliver enhanced performance for AI and HPC workloads. With the processor expected to debut in 2027, it will serve as a testbed for the commercial viability of high-density face-to-face chiplet stacking.

As the industry shifts towards leveraging packaging as a key driver of performance gains, the TSMC SoIC roadmap underscores the importance of vertical integration in advanced-node strategies. While the 2029 target for SoIC adoption does not guarantee universal implementation, factors such as cost, yield, thermal considerations, and design complexity will continue to influence the adoption of advanced packaging solutions. TSMC’s commitment to advancing chip-stacking technologies reflects a broader trend towards harnessing packaging innovations for enhanced performance and efficiency in semiconductor designs.