FPGA Synthesis for Dummies

Generic definition of Synthesis by Princeton University dictionary: The combination of ideas into a complex whole.

Even our FPGA synthesis tool does exactly that.

It combines our ideas (logic description) written in HDL into macros available in FPGA. However it is not a one-step process. Several optimization techniques are used.

Stages in FPGA Synthesis

Parsing – This is your HDL grammar teacher. Parsing searches for

syntax errors in HDL code. HDL parsing checks if the constants/signal/variables are defined, libraries declared, package declaration included, and all those minor details like begin, end, semicolons etc.

The check syntax button on Xilinx ISE performs parsing in the background. I believe Xilinx ISE tool uses a scripting engine in the background for parsing. Parsing, however, doesn’t check for the functionality. Your grammar teacher doesn’t know math/science.  

Macro Recognition–  This stage is very important for right inferring of your design. The HDL logic gets recognized as macros. Macros are digital logic building blocks like Gates, Registers, Latches, Multiplexers, Decoders, Three state buffers, Shift Registers, Accumulators, RAM etc. FSM is also recognized in this step. It is always recommended to read the user manual of Synthesis tool which prescribes coding style for proper inference of logic into macros, FSM.

Optimization  – Macros recognized in Synthesis stage are converted to blocks available in target FPGA device. Every FPGA has a set of components like RAMs, Shift Registers, Clock Buffers, Combinatorial  Logic, Multiplexers and Arithmetic Operations. User can add attributes and constraints for better control over optimization process. Constraints can be HDL specific, I/O specific, non-timing or timing specific.

Synthesis Goal

• Accurately infer the logic description
• Increase Maximum Clock Frequency of Design

In order to be a synthesis power user, we should make full use of the constraints, attributes, advanced synthesis options provided by FPGA vendor. Xilinx provides XCF file for user optimization.

This is a very brief introduction to Synthesis. There are more advanced synthesis optimization techniques for increasing the maximum clock frequency such as register balancing, register duplication etc. which can be discussed in another post.

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This is a guest post by Ravi Ramachandran, the article was first posted here.