August 30, 2019 — Intel today announced that it has begun shipments of the first Intel® Agilex® field programmable gate arrays (FPGAs) to early access program customers. Participants in the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. These customers are using Agilex FPGAs to develop advanced solutions for networking, 5G and accelerated data analytics.
“The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel® Xeon® processors with the upcoming Compute Express Link.”
–Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group
Why It’s Important: In the data-centric, 5G-fueled era, networking throughput must increase, and latency must decrease. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges by delivering significant gains in performance1 and inherent low latency. Reconfigurable and with reduced power consumption2, Intel Agilex FPGAs have computation and high-speed interfacing capabilities that enable the creation of smarter, higher bandwidth networks and help deliver real-time actionable insights via accelerated artificial intelligence (AI) and other analytics performed at the edge, in the cloud and throughout the network.
“Microsoft has been working closely with Intel on the development of their Intel Agilex FPGAs and we are planning to use them in a number of upcoming projects. Intel FPGAs have provided tremendous value for us for accelerating real-time AI, networking and other applications/infrastructure across Azure Cloud Services, Bing and other data center services,” said Doug Burger, technical fellow, Azure Hardware Systems at Microsoft. “We look forward to continued collaboration with Intel to deliver high-quality cloud services, big data analytics and ultra-intelligent web search results for our customers.”
How It’s Unique: The Intel Agilex family combines several innovative Intel technologies including the second-generation HyperFlex™ FPGA fabric built on Intel’s 10nm process, and heterogeneous 3D silicon-in-package (SiP) technology based on Intel’s proven embedded multi-die interconnect bridge (EMIB) technology. This combination of advanced technologies allows Intel to integrate analog, memory, custom computing, custom I/O and Intel eASIC device tiles into a single package along with the FPGA fabric. Intel delivers a custom logic continuum that allows developers to seamlessly migrate their designs from FPGAs to structured ASICs.
Intel Agilex FPGAs provide innovative new capabilities to help accelerate the solutions of tomorrow. Innovations include:
Design development for Intel Agilex FPGAs is available today via Intel® Quartus® Prime Design Software, which delivers the highest performance and productivity for Intel FPGA, CPLD, and SoCs.
The Small Print:
Further details on Intel Agilex performance, power and software support numbers:
1Up to 40 percent higher performance compared with Intel Stratix 10 FPGAs: Derived from benchmarking an example design suite comparing maximum clock speed (Fmax) achieved in Intel Stratix 10 devices with the Fmax achieved in Intel Agilex devices, using Intel Quartus Prime Software. On average, designs running in the fastest speed grade of Intel Agilex FPGAs achieve a 40 percent improvement in Fmax compared to the same designs running in the most popular speed grade of Stratix 10 devices (-2 speed grade), tested February 2019.
2Up to 40% lower total power compared with Intel Stratix 10 FPGAs. Derived from benchmarking an example design suite comparing total power estimates of each design running in Intel Stratix 10 FPGAs compared to the total power consumed by the same design running in Intel Agilex FPGAs. Power estimates of Intel Stratix 10 FPGA designs are obtained from Intel Stratix 10 Early Power Estimator; power estimates for Intel Agilex FPGA designs are obtained using internal Intel analysis and architecture simulation and modeling, tested February 2019.
3Up to 40 TFLOPs of DSP Performance (FP16 Configuration): Each Intel Agilex DSP block can perform two FP16 floating-point operations (FLOPs) per clock cycle. Total FLOPs for FP16 configuration is derived by multiplying 2x the maximum number of DSP blocks to be offered in a single Intel Agilex FPGA by the maximum clock frequency specified for that block.
Notices and disclaimers:
For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
Performance results are based on testing as of the dates set out above in the configurations, and may not reflect all publicly available security updates. See configuration disclosure for details. No product or component can be absolutely secure.
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com.
Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.