Alchip announces tape-out for 2nm process

Alchip Technologies Ltd. (Taipei, Taiwan) has said it has taped out a 2nm test chip and expects to see silicon back in the 1Q25.

The company also reports that it is actively engaged with customers on 2nm ASIC designs.

Alchip did not name the foundry but the company but given the emphasis on pioneering nanosheet and gate-all-around transistors there are strong indications that Alchip is working with TSMC’s 2nm process rather than Samsung or Intel. TSMC’s 2nm manufacturing process is the first node from that company to adopt a nanosheet gate-all-round (GAA) transistor structure, whereas Samsung introduced GAA at its 3nm node. At least for its own use Intel is reportedly skipping its 20A node and moving to 18A.

Alchip provides physical design and manufacturing services for digital CMOS ASICs and works with multiple foundries including TSMC, UMC, SMIC and Samsung but predominantly with TSMC.

The test chip features SRAM and silicon performance monitors to provide real-time insights and integrates shared and non-shared power domains and Alchip’s so-called lite I/O to test suitability for chiplets and 3D integration.

The test chip is therefore being used to establish the design flow and methodology for nanosheet transistor and will generate power, performance, and area (PPA) data for the 2nm process technology.

“We’re open for business and ready to serve customers’ 2nm demand. This test chip showcases our ability to push the boundaries of high-performance computing and artificial intelligence design,” said Erez Shaizaf, CTO of Alchip, in a statement.

Johnny Shen, Alchip’s CEO, added, “We’re looking forward to seeing how this breakthrough impacts the semiconductor industry.”