Analog Bits Advances to 2nm Power IP with 3nm Test Chips

Analog Bits, a leading semiconductor IP provider, is making waves in the industry by showcasing test chips for low drop out IP, power supply droop detectors, and embedded clock LC PLL’s in TSMC N3P process as part of its development of 2nm designs. This latest advancement builds upon the company's existing portfolio, which includes advanced IP for 4nm, 5nm, and automotive processes.

According to Mahesh Tirupattur, Executive Vice President at Analog Bits, the company's unwavering commitment to customer satisfaction and innovation has been instrumental in addressing the design challenges posed by 3nm and 2nm technologies. "Our ability to swiftly innovate and deploy cutting-edge IP solutions has not only helped in reducing system costs but also in enhancing overall performance," Tirupattur stated.

One of the key focuses for Analog Bits has been on managing power consumption in multi-core SoCs. To address this, the company has developed innovative LDO macros that can be easily scaled and shared among CPU cores. Additionally, their detector macros enable real-time monitoring of power supply health, allowing customers to optimize power distribution on the fly. This approach is akin to the stability provided by PLLs for clocking, but now applied to maintaining power integrity.

In a strategic move to bolster its engineering capabilities, Analog Bits recently inaugurated its Prague Design Centre in February, aligning with its 2nm development efforts. Tirupattur emphasized the company's track record of delivering top-tier IP solutions with exceptional performance and power efficiency. "Our success lies in recruiting top talent who are driven to make a difference. The expansion into Prague signifies a significant milestone in our growth trajectory and underscores our commitment to meeting customer needs," he added.

For more information on Analog Bits and its latest innovations in semiconductor IP, visit www.analogbits.com.