Arteris supports AI chip design with tiling/mesh network IP

Arteris Inc. (Campbell, Calif.) has added support for mesh networks and tiling of circuit arrays to its FlexNoC and Ncore products. This will provide support for developers of AI processing chips, the company said.

The addition of tiling and mesh support will allow systems-on-chip with AI to scale more easily, by up to a factor of 10, without requiring changes in the basic design. Support is included for turning tiles on and off dynamically, cutting power by 20 percent on average compared with simply leaving unused circuits dormant.

The mesh topology will support the faster development of AI and machine learning compute in SoC designs, Arteris said. The company claims that subsystem design time and overall SoC connectivity execution time can be trimmed by up to 50 percent compared with manually integrated non-tiled designs.

The first iteration of NoC tiling organizes Network Interface Units (NIUs) into modular, repeatable blocks.

“Arteris is continuously innovating, and this revolutionary NoC soft tiling functionality supported by large mesh topologies is an advancement in SoC design technology,” said Charles Janac, CEO of Arteris, in a statement. “Our customers, who are already building leading-edge AI-powered SoCs, are further empowered to accelerate the development of much larger and more complex AI systems with greater efficiency, all while staying within their project timeline and PPA targets.”

Srivi Dhruvanarayan, vice president of hardware engineering at Sima Technologies Inc. (San Jose, Calif.), said: “We look forward to deploying the expanded Arteris NoC tiling and mesh functionality, which should further enhance our ability to create highly scalable AI silicon platforms for the edge.”

The FlexNoC and Ncore NoC IP products with expanded AI support via tiling and extended mesh topology capabilities, are now available to early-access customers and partners.