DeepX plans 2nm edge AI chip

DeepX, a company based in Korea, is currently in the process of designing an edge AI chip that boasts a remarkably low power consumption of just 5W. This cutting-edge chip is set to be constructed using the advanced 2nm process technology at Samsung Foundries. Additionally, DeepX is exploring the possibility of creating a chiplet version of this innovative chip.

The DX-M2, as it is known, is being developed with the goal of achieving a performance level of 40TOPS. It is being specifically optimized to efficiently run transformer models like GPT and various AI agents. The chip will have the capability to handle models with up to an impressive 20 billion parameters, enabling functionalities such as integrating natural language chat features into embedded devices like vending machines and humanoid robots. To manage the scheduling, a custom RISC-V processor will be incorporated into the design.

Preceding the DX-M2 is the DX-M1, a chip with a performance of 25TOPS that is currently being manufactured on a 5nm process. Scheduled to enter mass production in the first half of 2025, the DX-M1 is tailored for video processing tasks, utilizing a combination of floating point and 8-bit integer (INT8) weights. This chip is also being utilized in AI PCs and edge servers. Tim Park, the strategic marketing director at DeepX, emphasized the importance of mixed precision in the design process to optimize performance.

With a total funding of $531 million secured thus far, DeepX has garnered support from Hyundai Robotics. Park mentioned that the company is now in the phase of scaling up its operations. The DX-M1, designed primarily for vision applications, has been employed in collaboration with automotive giants like BMW, Mercedes, and Volkswagen for vision-related tasks in autonomous driving applications. DeepX has gained valuable insights into the automotive market through these collaborations and is now exploring opportunities in the heavy vehicle market.

Looking ahead, DeepX is gearing up to introduce a second version of the chip, the V3, which will feature a system-on-chip design. This iteration will incorporate four ARM Cortex-A53 cores alongside the NPU of the M1, along with an image signal processing block. Targeted at still cameras and mid- to high-end IP cameras, the V3 will be capable of handling vision models with parameters ranging from 150 million to 200 million, all at an affordable price point of around $20. The sampling for this version is expected to commence in August.