First Ultra Ethernet, UALink IP

Synopsys has launched the industry’s first Ultra Ethernet IP and UALink IP for standards-based, high-bandwidth, and low-latency HPC and AI accelerator interconnect.

The IP includes controllers, PHYs, and verification IP for chips that have to handle trillions of parameters in the next generation of AI models.

The Ultra Ethernet and UALink IP will provide a holistic, low-risk solution for high-speed and low-latency communication to scale-up and scale-out AI architectures with up to 1024 accelerators and up to a million end points.

The silicon-proven 224G Ethernet PHY IP, which supports the Ultra Ethernet protocol, has been demonstrated with broad interoperability. The Ultra Ethernet MAC and PCS controller IP provides up to 1.6 Tbps of bandwidth with ultra-low latency, enabling the real-time processing needed for AI workloads through a patented error correction scheme. These support an interface to the higher layers of the Ultra Ethernet stack providing a full silicon implementation for switches, AI accelerators and smart NICs.

“For more than 25 years, Synopsys has been at the forefront of providing best-in-class IP solutions that enable designers to accelerate the integration of standards-based functionality,” said Neeraj Paliwal, senior vice president of IP product management at Synopsys. “With the industry’s first Ultra Ethernet and UALink IP, companies can get a head start on developing a new generation of high-performance chips and systems with broad interoperability to scale future AI and HPC infrastructure.”

“Juniper has already introduced the industry’s first 800GbE capability with its PTX10002-36QDD Packet Transport Router, which utilizes our proprietary Express 5 ASIC with Synopsys Ethernet IP,” said Debashis Basu, senior vice president of Juniper Engineering. “We will continue to partner with Synopsys and leverage the latest technologies from the Ultra Ethernet Consortium (UEC) to transition into the 1.6TbE era. This indicates our ongoing innovation in high-speed networking to achieve our goal to significantly improve scale, reliability, and performance in data center networks. This is particularly important as AI workloads continue to grow exponentially, making such networks much more efficient and cost-effective.”

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The UALink PHY IP provides 200 Gbps per lane to mitigate critical bottlenecks of AI hardware infrastructure via shared memory access from accelerator to accelerator. The UALink Verification IP, combined with Synopsys hardware-assisted verification solutions, provides quick and reliable verification for AI hardware. 

“Synopsys has decades of expertise in contributing to the industry’s essential interconnect standards and in delivering widely adopted high-speed interface IP,” said Kurtis Bowman, chairperson of the board at UALink Consortium. “We appreciate Synopsys’ commitment to enabling UALink IP to create a scalable, high-performance data center ecosystem for designers to meet the growing demands of AI models.”

“Advancing AI technology requires industry-wide efforts to create high-performance solutions essential for the future of data centers,” said Robert Hormuth, corporate vice president, architecture and strategy, data center solutions group at AMD. “The introduction of Synopsys’ Ultra Ethernet and UALink IP, alongside AMD high-performance processors, highlights the commitment to create an open, robust, and scalable ecosystem for large-scale AI and high-performance computing.”

“The progress of AI technology relies on industry collaboration to deliver scalable and power-efficient high-performance accelerator fabrics,” said Chris Petersen, fellow, technology and ecosystems at Astera Labs. “New interconnect technologies such as UALink will help support the rapid growth and complexity of AI and HPC workloads. We congratulate Synopsys on the delivery of its new IP solutions to enable this critical connectivity ecosystem.” 

“Participating in defining and developing an open standards-based AI systems communications is an important part of Tenstorrent’s charter. The low latencies and high bandwidths of the upcoming UEC and UALink standards will enable ultra-efficient interfaces supporting AI compute with multi-trillion parameter models,” said David Bennett, chief customer officer at Tenstorrent. “Tenstorrent’s RISC-V chips and Synopsys’ new UALink and Ultra Ethernet IP will enable the largest AI accelerator clusters.”

“To keep pace with the exponential growth in AI model parameters and compute requirements, hyperscalers need to address immense connectivity challenges,” said Gerry Fan, CEO at XConn. “With XConn’s UALink switches and Synopsys’ new UALink IP, system architects can deploy high-performance, standards-compliant systems for future AI computing and networking architectures.”

The Synopsys Ultra Ethernet IP solution, including MAC and PCS, PHY, and verification IP, is scheduled to be available in the first half of 2025. The Synopsys UALink IP solution, including controller, PHY, and verification IP, is scheduled to be available in the second half of 2025.