Innoscience Seeks USPTO Ruling on Infineon GaN Patent

Infineon's US Patent No. 9,899,481 lies at the center of legal disputes initiated by Infineon against Innoscience in both the United States and Europe. Innoscience Technology Co. Ltd., based in Zhuhai, China, has raised concerns regarding the validity of the patent in question, contending that it pertains to the packaging of GaN transistors rather than fundamental aspects of GaN power semiconductors.

Innoscience has taken a proactive step by formally requesting the US Patent and Trademark Office (USPTO) to conduct an 'inter partes' review of the patent's validity. The objective is to invalidate all claims within the '481 patent. In its petition against Infineon's patent, Innoscience asserts that the claims can be refuted based on evidence of prior art or obviousness.

Furthermore, Innoscience has expressed its intention to challenge the validity of three German patents owned by Infineon. The company maintains that the legal actions in the US and Europe are limited to a small portion of its GaN transistors and do not impede its ability to manufacture, sell, or distribute products to customers until a final judgment is reached.

Established in December 2015, Innoscience proclaims itself as the largest producer of GaN-on-Si power transistors globally. The company inaugurated its initial 200mm wafer fabrication facility for GaN-on-Si production in Zhuhai in November 2017, followed by a second facility in Suzhou in September 2020. Innoscience boasts a portfolio of over 800 patent applications worldwide and maintains a research and development team comprising more than 500 engineers.

For more information, visit the official websites of Infineon and Innoscience. Stay updated on the latest developments in the legal dispute between Infineon and Innoscience:

• Infineon sues Innoscience over US GaN patents – update
• China's Innoscience responds to Infineon's European GaN lawsuits
• China's Innoscience denies EPC claims of GaN patent infringement
• Innoscience appoints former senior NXP engineer to lead R&D