New Network-on-Chip Technology for Arm v9 Architecture and Automotive Safety

Arteris has announced the release of version 3.6 of its Ncore cache coherent network-on-chip, which now supports Armv9 automotive cores and ASIL D functional safety. This development comes as a result of the partnership between Arteris and Arm, with a focus on aligning roadmaps to meet the evolving needs of the industry.

According to Arteris, the expansion of the partnership includes a pre-validation of their Ncore interconnect intellectual property with Armv9 cores. Ncore is now equipped to meet the ISO 26262 requirements from ASIL B to ASIL D for automotive and other mission-critical systems. This move underscores Arteris' commitment to providing cutting-edge solutions for the automotive sector.

One of the key features introduced in Ncore v3.6 is the support for CHI-E, a fully coherent agent interface for AMBA busses. This addition complements the existing CHI-B and ACE interfaces in Ncore, offering a comprehensive solution for system coherence. Additionally, the inclusion of ACE-Lite for IO coherency and AXI further enhances the versatility of Ncore.

The upgraded replacement policies for caches in Ncore v3.6 now include PLRU (pseudo least recently used) and NRU (not recently used), providing more flexibility and efficiency in managing cache memory. Moreover, the debug interfaces have been enhanced to AMBA APB4, while Ncore's functional safety control now supports parity bits to protect registers, ensuring robust safety mechanisms.

Charles Janac, CEO of Arteris, highlighted the challenges faced by SoC designers in navigating the complexities of modern electronics. With the latest release of Ncore, Janac emphasized the company's commitment to simplifying the design process and enabling seamless connectivity for any processor, using any protocol and topology. This milestone represents a significant step towards achieving Arteris' vision for the future of system-on-chip design.