OpenLane Successor for Open Source Chip Design

The FOSSi Foundation has launched the successor to OpenLane EDA toolflow for open source chip design.

LibreLane is a ground-up redesign of OpenLane with compatible flows that can freely be created, customised, and distributed. It uses a Python-based infrastructure for the implementation of highly customisable and repeatable ASIC flows.

The default Classic flow replicates OpenLane near-perfectly, even supporting the very same configuration files, but also allows unparalleled flexibility by allowing people to write fully-custom advanced data-flows.

OpenLane, released by now defunct eFabless, combined existing projects including Yosys, OpenROAD, Magic and KLayout to create an RTL-to-GDSII flow that was configurable with just one file. It was used with the SkyWater 130nm silicon process and Pragmatic Semi plastic process.

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“Back at Efabless, as early as 2022, my colleagues Kareem Farid, Mohamed Shalan and I started a project to rewrite OpenLane that we simply titled OpenLane 2,” said the developer Mohamed Donn Gaber.

“OpenLane 2 was a ground-up rewrite of OpenLane, with the goal of continuing to support OpenLane configuration files, but providing far more flexibility and consistency than OpenLane ever did. OpenLane 2 was soft-launched at Efabless in February 2024, but we waited patiently to get silicon with strict timing requirements back to verify STA quality of results until we could officially recommend the new flow to our then-customers. About a year later, we did the tests in question, but due to funding challenges, Efabless shut down just days after.

He has since joined the Free Open Source Silicon (FOSSi) Foundation to maintain the tool.

“We designed LibreLane with three goals in mind,” he said. “The first and most important principle is to retain the ease-of-use for OpenLane: Like OpenLane, LibreLane allows flows to be configured entirely with one Tcl, JSON or YAML file that allows you to get from RTL-to-GDSII. [However] setting LibreLane apart from OpenLane, we wanted a well-documented API with which users can create their own flows.”

The core idea LibreLane was built around was an explicit representation of the current state of a design. It defines the state of a design as a simple object that stores paths to various files representing the design: netlists, design exchange format (DEF) files, JSON netlists, etc, in addition to a collection of metrics. The design__die__area metric, for example, returns the area of the design in square microns. These objects are immutable, meaning they cannot be modified, only copied, and are fully serialisable to JSON for traceability, so they may be saved at multiple points in the flow to show how a flow has progressed.

To do EDA tasks, Steps are essentially functions that take in one state, and output another state. For example, the Floorplan Step takes a State with a Netlist, and creates a new State with a DEF file. The Routing Step takes a State with a DEF file, and creates a new State with a new DEF file.

“By modeling EDA tasks like this, we were able to make the steps highly repeatable, as no global database is being mutated, but it also allows flows to try to explore multiple configurations in parallel by running multiple steps on multiple threads,” said Donn Gaber.

Flows are aggregations of steps. They can be simple, serial SequentialFlows, running one step after another, or fully custom functions that do things like the aforementioned parallel exploration. Flows provide simpler configuration and the ability to more easily control the execution from the command-line, which is more difficult when running step by step.

Finally the Config module is responsible for exposing all the various input configuration variables) of steps to the user, allowing them to configure the flow using Tcl, JSON, or YAML files, as well as using a Python dictionary. The Configuration module also handles validation and type-checking, which was a pain point with OpenLane where the flow would simply crash at an undetermined point if an input variable happened to be invalid. As with States, Configs are also immutable and cannot be modified after the fact, though flows may create derivative configurations to feed different steps slightly different configurations.

A aspect of the tool is that it allows other tools to be incorporated. Designers at eFabless used the flow with the Synopsys Design Compiler and PrimeTime tools using custom steps to squeeze just a bit more performance out of chip designs.

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Tiny Tapeout has also used custom LibreLane-based flows to implement the top-level multiplexer for Tiny Tapeout 3.5 and as the ASIC implementation backend for every subsequent digital Tiny Tapeout project. LibreLane has already found its way into academic projects including Greyhound and Piel. Importantly, ChipFoundry, as agreed to adopt LibreLane as their primary flow as of their ChipCreate CC2509 shuttle, continuing OpenLane’s legacy in enabling the commercialisation of open-source EDA technology.

LibreLane 2.4.0, the first version after the fork and rename, is available for macOS and Linux (and Windows with WSL2). The getting started guide shows you how to install all requisite dependencies.

github.com/librelane/librelane