Superconducting CMOS gives AI chip power boost

imec in Belgium has shown key superconducting building blocks in CMOS for building AI and high performance computing (HPC) systems with dramatically lower energy.

The three critical building blocks of a superconducting CMOS digital circuits were shown at 2024 IEEE International Electron Devices Meeting (IEDM). These cover NbTiN-based interconnects, Josephson junctions, and MIM capacitors. The devices outperform current superconducting technology and meet the target specifications for superconducting digital systems designed to revolutionize the roadmaps for AI and HPC.

Compute systems based on superconducting digital technology promise to significantly outperform CMOS-based processors by taking advantage of the zero electrical resistance of the superconducting materials at cryogenic temperatures.

The proposed technology can withstand conventional back end of line (BEOL) processing temperatures of 420°C and is compatible with standard 300mm CMOS processing.

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A system-technology co-optimization study showed that first-generation superconducting digital systems deliver 100x more system power efficiency and 10-100x better performance than a 7nm-CMOS-based system. To meet these target system specifications, a  scalable technology is needed to fabricate the key building blocks of such superconducting digital circuits: superconducting interconnects (wires and vias), Josephson junctions serving as the active elements, and tunable MIM capacitors for power delivery.

For the superconducting interconnects, a semi-damascene integration process was used to build a two-metal-level scheme with wires and vias having critical dimensions down to 50 nm. Measurements at cryogenic temperatures reveal a critical temperature larger than 13K and a critical current density Jc>120 mA/µm2 – a world record at such a small scale.

The Josephson junctions, with amorphous Si (aSi) sandwiched between two superconducting NbTiN layers, exhibit record-high Jc>2.5 mA/µm2. imec researchers also demonstrated tunable HZO-based capacitors with NbTiN electrodes, having a high capacitance density of ~28 fF/µm2. With these characteristics, all three modules meet the process specifications.

“Key to the outstanding results is the adoption of novel integration schemes in combination with NbTiN, a superconducting material with much better scaling potential than Nb,” said Anna Herr, scientific director at imec USA Florida.

“The technology is scalable to high device densities, already exceeding superconducting state-of-the-art with 500x. imec’s semi-damascene integration scheme is expandable to multiple metal levels. It lays the foundation for building a 16-metal-level interconnect fabric in which the junctions and capacitors must be embedded to benefit from the zero-wire resistance. We believe that our demonstration is a crucial step towards industrial processing in commercial foundries,” she added.