Synopsys brings GenAI capabilities to EDA

Synopsys has enhanced its Synopsys.ai Copilot generative AI (GenAI) capabilities to further support semiconductor design solutions, providing semiconductor engineering teams with the tools to expedite development timelines, handle more complex designs, and enhance capabilities in the face of a workforce shortage.

The GenAI capabilities offered by Synopsys help customers enhance silicon performance, boost efficiency, and speed up time to market. These expanded capabilities have already been put to use by early access customers, showcasing significant improvements in design quality and engineering productivity. Workflows that previously took days are now being completed in hours, and tasks that used to take hours are now accomplished in minutes.

Sanjay Bali, Senior Vice President of Strategy and Product Management at Synopsys, emphasized the impact of AI on chip design, stating, "AI is revolutionizing every layer of chip design and fueling a wave of ingenuity to deliver the next generation of advanced SoCs." With the latest capabilities of Synopsys.ai Copilot supporting assistive and creative applications throughout the chip design process, engineering teams are empowered to enhance design quality, free up time for high-value opportunities, and accelerate technology innovation.

Assistive GenAI capabilities provided by Synopsys are being utilized by top customers through breakthrough knowledge assistant and workflow assistant applications. These tools enable engineers to work more efficiently and quickly with Synopsys tools, resulting in a 30% faster ramp time for early-career engineers. Tasks such as documentation searches and script generation that previously took hours can now be completed in minutes with Synopsys.ai Copilot.

Moreover, the knowledge assistant application is now accessible to all Synopsys Cloud users, whether on SaaS or Bring Your Own Cloud (BYOC) deployments. This integration is particularly beneficial for startups hosted on the Synopsys Cloud SaaS platform, allowing them to enhance engineering productivity and expedite time-to-tape out with seamless access to the knowledge assistant application.

Creative GenAI capabilities from Synopsys, such as formal assertion generation and RTL code generation, are aiding early access customers in accelerating design and verification cycles. For instance, a leading AI infrastructure solutions provider experienced a 35% increase in engineering productivity within formal verification workflows, thanks to automated formal testbench creation. This efficiency boost enabled the team to validate 10 design components in just 10 days.

The introduction of Ansys Engineering Copilot by Ansys, now part of Synopsys, is another significant development. This virtual assistant is designed to shorten learning curves, enhance engineer productivity, and speed up the use of Synopsys simulation tools. Ansys SimAI, a physics-agnostic application, has also been updated to integrate with Ansys optiSLang®, facilitating faster dataset creation and AI training to enable more efficient design variation exploration and shorter product development cycles.

Synopsys is paving the way for the future with its GenAI capabilities, laying the groundwork for AgentEngineer technology in chip design. These agents and multi-agent systems are tailored to improve engineering workflows by introducing levels of autonomous execution, ultimately boosting productivity, improving results, and reducing computational requirements. Through a close collaboration with Microsoft, Synopsys showcased the first prototype of AgentEngineer technology at DAC 2025, signaling a new era of agentic AI.

Aseem Datar, Corporate Vice President of Product Innovation at Microsoft, highlighted the transformative nature of their collaboration, stating, "Together, we are not just optimizing existing workflows — we are introducing a new paradigm to advance engineering innovation and productivity for next-generation chip designs." The vision for AgentEngineer technology is to progress from performing step-level actions to autonomous decision-making, reshaping the landscape of chip design innovation.