Synopsys Utilizes Rapidus Data for AI Chip Design Flow

Rapidus in Japan has recently entered into a groundbreaking agreement with Synopsys to revolutionize the design flow by incorporating artificial intelligence (AI) to model process sensitivity and variation. This innovative approach aims to enhance efficiency and reduce costs in semiconductor design.

Specifically, the new AI approach developed by Synopsys will be utilized by Rapidus for nodes as advanced as 2nm and below. By leveraging AI technology, the need for costly re-characterization of libraries and memories will be significantly minimized, leading to more streamlined design processes.

Under the terms of the agreement, Synopsys will focus on creating advanced design flows using its AI-driven Electronic Design Automation (EDA) suite. This collaboration will also involve enabling a wide range of intellectual property (IP) on the Rapidus 2nm Gate-All-Around (GAA) process.

The joint effort will support Rapidus' initiative on Design for Manufacturing and Co-Optimization (DMCO), which aims to optimize both design and manufacturing processes simultaneously. By combining Manufacturing for Design (MFD) with traditional Design for Manufacturing (DFM) techniques, the integration of sensors and AI in the wafer process will facilitate the efficient design based on data obtained during manufacturing.

Moreover, the partnership will integrate Rapidus' extensive big data resources into Synopsys' AI-driven EDA flows to implement MFD for the benefit of mutual customers. This strategic alignment is expected to enhance design support and accelerate the path to successful silicon implementation.

Rapidus will also leverage Synopsys' portfolio of interface and foundation IP tailored for its process technologies to mitigate integration risks and expedite the journey to silicon success. The Rapid and Unified Manufacturing Service (RUMS) initiative by Rapidus is designed to reduce time-to-market for customers by offering comprehensive design support across front-end and back-end processes.

One of the critical challenges in semiconductor design cycle time is the characterization of IP libraries, which often necessitates recharacterization with each update of the process design kit (PDK) or manufacturing process. This time-consuming process can significantly impede design progress, taking months to generate a timing model.

To address this bottleneck, the DMCO flow will incorporate PrimeShield, a machine learning-based timing model generation tool that utilizes sensitivity libraries. By calibrating with silicon data from Rapidus' manufacturing process, model accuracy will be enhanced, leading to faster design convergence.

Dr. Atsuyoshi Koike, CEO of Rapidus, expressed optimism about the partnership with Synopsys, emphasizing the potential to simplify and expedite the design process. He highlighted the vision for RUMS to utilize a single-wafer front-end process, aligning with Synopsys' AI-driven EDA flows and IP to achieve rapid production.

Sassine Ghazi, president and CEO of Synopsys, underscored the company's pivotal role in enabling leading foundries and facilitating advanced design solutions. The collaboration with Rapidus is set to empower designers to achieve optimal quality results and high manufacturing yield for the cutting-edge 2nm GAA process.

For more information, visit www.rapidus.com and www.synopsys.com.