TSMC drives A16, 3D process technology

TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.

The Open Innovation Platform (OIP) meeting in the Netherlands this week showed that the 2nm process will be in production in 2025 following early tapeouts this year, with a variant called N2P nanoFlex with the option for short standard cells for smaller area and greater power efficiency or tall cells for more performance. 

This will give a 12% boost in energy efficiency over the base 2nm process, while A16 will give a 30% boost with the same density as N2 nanoFlex. Both TSMC and Intel are detailing their 2nm technologies at the IEDM conference in December.

New place and route algorithms have been developed for N2 and N2 nanoflex, while the A16 adds a ‘super power rail (SPR) to provide power from the back of the wafer for AI and high performance chip design. This also requires more P&R optimisation in the EDA tools from Synopsys and Cadence Design Systems.

A Project Authorization Request review is underway for the standardisation of 3Dblox, with IEEE P3537 number, and an official announcement is expected by December 2024. There have also been a number of enhancements for the process (see below).

Cadence has a full design flow for A16, while the multi-physics analysis tools from Ansys are key for the design flow from Synopsys, which is in the process of acquiring Ansys.

A 3D system on integrated chips (SoIC) process will be key for 2nm and 16A designs, says TSMC.

“We are on the brink of an AI-driven era, with soaring demand for high-performance AI chips in data centres,” said Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC. “We are using AI and machine learning to significantly improve 3D IC design productivity and optimize design power, performance, area (PPA), and quality of results (QoR),” he said.

“TSMC’s 2nm technology provides superior performance and energy efficiency, along with its 3DFabric, driving Socionext’s 3D IC innovations to offer scalable solutions for variety of applications including data centers, 5G/6G infrastructure, and edge computing. TSMC’s technology and its comprehensive ecosystem help Socionext significantly reduce the time to deliver competitive products to the market,” said Hisato Yoshida, deputy president and head of Global Development Group at Socionext

Advanced 3D stacking chips will be integrated in the 2.5D CoWoS process for next-generation AI compute, while a 9-reticle CoWoS featuring SoIC and 12 HBM4 memory chips is targeted to be qualified in 2027, up from 5.5 reticle devices using 2nm and 3nm chips in 2025.

“Broadcom completed the successful bring-up of Industry’s first Face-to-Face 3D SoIC in September 2024. This device uses TSMC’s 5nm Process, 3D die-stacking and CoWoS packaging technologies to integrate 9 die and 6 HBM stacks in a large package. This paves the way for a number of 3D-SoIC production ramps expected in 2025. Broadcom continues to use 3Dblox which is a welcome advancement for interoperability of EDA tools in 3D IC design flow,”  said Greg Dix, vice president, R&D & Engineering, ASIC Product Division, Broadcom –

3Dblox

The latest version of 3Dblox has further evolved to effectively tackle large 3D IC design with early planning capabilities.

EDA AI engines can fully explore the electrical and physical design space, the complex 3D IC design can be efficiently and successfully divided into individual 2D IC designs to maximize productivity. Thermal coupling means a 3D IC system has stronger dependencies among timing, power, electromigration/IR drop (EMIR), and thermal analysis. Multi-physics analysis greatly reduces setup effort through a seamless integration of multiple analysis engines under the same database that allows easier data passing and precise convergence control.

Early Floorplan Design Rule Check (DRC): Rotation, flip, and projection of chiplets is a complex process that can make DRC complicated under the 3D context. This new feature identifies key 3D floor-planning rules that are essential for a correct floorplan, thereby effectively decoupling the planning from the final implementation checks.

Auto Alignment Marks Insertion: As the size of 3D integration grows, more alignment marks are needed for process control purposes. TSMC enables a fully automated correctby-construction flow that takes away the complexity of calculating the coordinates of each alignment mark though chiplet rotation, flip, projection, or optical shrink. This new approach has tremendously simplified the alignment mark insertion flow.

3Dblox Common Constraints for Early Chip-Package Co-Design: The industry lacks common protocols in the early phase of chip-package co-design. The 3Dblox Common Constraint Format bridges the gap by providing a formal definition of the needed constraints to facilitate precise communication between teams and ensure the rapid convergence of package and integration rules.

TSMC is working with partners to apply Generative AI to enhance design productivity, using large language models (LLMs) for workflow, run assistant flow script and Register-Transfer-Level (RTL) design and debugging, as well as for knowledge assistant tool and usage flow enquiries. This approach helps significantly increase design productivity, speeding up the process from an idea to a successful design.

It is also working with electronic design automation (EDA) partners to apply AI in design works for digital design metal scheme optimization, cell library and EDA setting optimization, analog design migration, analog circuit optimization, and 3D IC design space exploration. The AI-driven workflow streamlines the floor planning process to optimize for thermal, signal, and power integrity, thereby maximizing system performance and QoR.

“Our collaboration with TSMC on advanced silicon solutions for our AWS-designed Nitro, Graviton, Trainium, and Inferentia chips enables us to push the boundaries of advanced process and packaging technologies, providing our customers with the best price performance for virtually any workload running on AWS,”  said Gary Szilagyi, vice president of the Annapurna Labs chip design subsidiary of Amazon

“These approaches highlight just a few examples of how we are working closely with our OIP partners to enable the future of AI chip designs from analog design migration to 3D IC design space exploration,” said Kochpatcharin at TSMC.