UCIe IP subsystem supports 36G die-to-die data rates

Alphawave Semi Achieves Milestone with Tape-Out of UCIe IP Subsystem on TSMC N2 Process

Alphawave Semi has announced the successful tape-out of its UCIe IP subsystem on the TSMC N2 process, supporting 36G die-to-die data rates. The IP is fully integrated with Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology from TSMC, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone, building on the recent release of the Alphawave Semi AI Platform, demonstrates readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the first to enable UCIe connectivity on 2nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

“Our 36G subsystem validates a new class of high-density, power-efficient chiplet connectivity and paves the way for 64G UCIe and beyond—critical for AI and high-radix networking applications,” said Mohit Gupta, Senior VP and GM, Custom Silicon and IP, Alphawave Semi.

The UCIe IP subsystem provides 36G performance with 11.8 Tbps/mm bandwidth density, ultra-low power and latency, along with advanced features such as live per-lane health monitoring and comprehensive testability. Compliant with the UCIe 2.0 standard, the subsystem supports multiple protocols, including PCIe, CXL, AXI, CHI, and more, using Alphawave Semi’s highly configurable and efficient Streaming Protocol D2D Controller.

Alphawave Semi is advancing key ecosystem collaborations to enable groundbreaking technologies, leveraging D2D-based open chiplet interoperability to drive a broader AI connectivity platform for the industry.

“Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design that fully leverage the performance and energy-efficiency advantages of TSMC’s advanced process and packaging technologies,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “This milestone illustrates how close collaboration with our Open Innovation Platform® (OIP) partners like Alphawave Semi can enable the quick delivery of advanced interface IP and custom silicon solutions to meet the increasing demands of AI and cloud infrastructure.”

Alphawave Semi is already executing its plans to deliver next-generation UCIe, with 64G UCIe support, empowering AI and HPC customers to lead in a rapidly evolving chiplet-driven landscape.