Agile Analog Introduces IP Subsystem for SoC Sleep Mode

Agile Analog, a leading customisable analogue IP company, has recently unveiled its groundbreaking always-on IP subsystem designed to enable an ultra-low-power sleep mode for the latest generation of System on Chips (SoCs).

Working closely with XMOS, Agile Analog integrated a range of analogue IP blocks into a single macro, complementing XMOS's digital control system to create a comprehensive always-on subsystem. This collaboration marks a significant milestone in the development of energy-efficient solutions for modern semiconductor devices.

The suite of ultra-low-power IP components provided by Agile Analog includes the agileREF configurable bandgap reference, agilePOR power-on-reset, agileRCOSC oscillator, agileCMP comparator, and agileLDO capless LDO. These components collectively contribute to minimizing power consumption and enhancing the overall efficiency of the SoCs.

Barry Patterson, the CEO of Agile Analog, expressed his enthusiasm for the project, stating, "This project exemplifies the capabilities of our Composa technology and underscores our dedication to fostering strong partnerships with our clients." The Composa technology streamlines the process of generating analogue IP tailored to specific foundries and processes, offering customers the flexibility to customize the IP to meet their exact specifications for optimal performance and power efficiency.

In response to the growing demand for always-on IP solutions, driven by the proliferation of smart wearable devices and remote monitoring systems, Agile Analog's latest innovation is poised to address the need for devices to maintain a low-power state for extended periods while being able to quickly resume operation when necessary. Chris Norrison, a key figure at Agile Analog, emphasized the importance of the always-on IP subsystem in enabling energy-efficient and responsive SoCs essential for the next generation of smart devices.