Avnet ASIC Introduces Low Power 4nm Design Service

The ASIC design division of distributor Avnet Silica has introduced a new service offering for low power 4nm custom chips at TSMC. This move is part of Avnet's strategic focus on catering to TSMC's advanced process technologies, specifically targeting the 4nm process and below for custom blockchain and AI edge computing applications. Avnet's ASIC design service has been expanding its presence, with operations in Europe since 2019, following its establishment in Israel back in 1986.

The newly launched design services are tailored to address the challenges of operating under low-voltage conditions in the 4nm and below nodes. Avnet's approach includes recharacterizing standard cells for lower voltages, conducting early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and leveraging transistor-level simulations to enhance the power optimization process.

The Avnet ASIC team has developed a comprehensive design flow focused on PPA optimization for high-performance chips that operate at extremely low voltages, successfully demonstrating its capabilities in TSMC's 4nm process. Through post-silicon validation with a customer, the team has validated performance, dynamic, and leakage power estimations, showcasing the effectiveness of their design methodologies.

Working closely with customers, Avnet ASIC collaborates on defining board solutions and chip implementation concepts, requirements, and executing front-end designs based on library characterization for near-threshold voltage operation. This customer-centric approach ensures that the final chip design aligns with the specific needs and objectives of the client, enhancing overall project success and efficiency.

In a recent development, the Avnet ASIC team was appointed as a Value Chain Aggregator (VCA) by TSMC, solidifying its position as a key channel for TSMC ASIC customers. This appointment enables Avnet ASIC to offer end-to-end solutions, from design inception to layout and mass production, utilizing an EDA tool flow from Synopsys. This strategic move enhances Avnet's competitiveness in the ASIC design space, positioning it as a comprehensive service provider for customers seeking advanced semiconductor solutions.