EV Group Enhances Digital Lithography for AI Chiplet Packaging

The EV Group in Austria has developed a maskless digital lithography system that is five times faster than previous systems for high volume AI chiplet assembly.

The Lithoscale XT maskless exposure (MLE) system supports heterogeneous integration applications such as chiplets and high bandwidth memory without needed expensive masks and the limitation of the reticle size of the mask.

However digital direct write laser systems have been slower for lithography, limiting the use in high volume manufacturing. Now the higher throughput comes from a dual-stage design with up to six exposure units to write the patterns into the resist with a dual-wavelength direct laser source.

This is used for multi-die patterning, fan-out wafer-level packaging (FoWLP) for AI and high-performance computing (HPC) devices, panel-level packaging, MEMS, advanced imaging sensors, and die traceability for security and automotive applications.

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Heterogeneous integration of different dies into a single package has led to greater package complexity, as well as a greater number of package options available. This in turn is driving the need for greater design flexibility and the ability to adopt both die-level and wafer-level designs simultaneously in back-end lithography.

Accurate reconstitution of wafers is a key parameter in integrating dies from various wafer fabs or fab lines in multi-die solutions. Steppers and other mask-based patterning systems struggle to cope with inaccuracies from die-placement and die-shift variations caused by over-molding.

In addition, the reticle size and optics dimensions of static exposure systems limit the exposure area. This is particularly challenging in large die interposer fabrications, where stitch-lines and/or mismatches overlap regions of the reticle exposure field, which can affect the electrical properties within the redistribution layer (RDL).

The ability to generate a homogenous pattern for interposers that exceed current reticle size is crucial for devices with complex designs, such as those used for GPUs such as Nvidia’s Blackwell and Rubin for AI as well as for 5G and AI chiplet packages for high performance computing (HPC).

The updates to the hardware and software enable real-time data and immediate exposure, with high structuring resolution and high throughput with up to six exposure heads covering a 300-mm wafer or 300-mm x 300-mm panel substrate in a parallel exposure process.

The dual-wavelength laser source supports both thin and thick photoresists, 100 microns in thickness as well as chemically amplified resists, positive and negative tone, dielectrics and high-aspect-ratio patterning.

The resolution is under 2 micron lines/spaces, with stitch-free, full wafer patterning with no field-exposure or die-size limitations and there is simple switching between mask layouts without the associated high costs of having many masks in a set.

The real-time data compensates for wafer-level distortion and die-shift for bowed or warped wafers, enabling improved die-placement accuracy and patterning yield without impact on throughput supporting multi-die patterning.

The real time data is also used for Dynamic Die Annotation that generates unique die identifiers for each individual wafer on the fly, supporting industry standards for individual die identification and traceability—such as SEMI E142 and SEMI T23—that are designed for security and automotive markets.

“The adoption and evolution of heterogeneous integration is driving tighter performance requirements for back-end lithography that can no longer be fully met with traditional mask-based solutions like steppers and mask aligners,” said Dr. Bernhard Thallner, pathfinding and optics director at EV Group.

“While the technical advantages of MLE technology are abundantly clear, throughput has been a barrier to HVM adoption until now. The latest MLE platform supports the unique patterning needs in HVM, not only for advanced packaging but also numerous other applications that can benefit from its combination of high versatility, resolution and throughput.”

As well as AI chiplet packaging, digital lithography is used for the manufacture of image sensors where the complex shapes and highly functional optical materials present challenges to stepper technologies. These are addressed with the high resolution and improved sidewall profile performance on structures with complex shapes and/or high aspect ratios.