Exploration platform for RISC-V CHERI designs

European RISC-V core developer Codasip has introduced a new FPGA-based ‘exploration platform’ centered around its X730 core, which incorporates the CHERI (Capability Hardware Enhanced RISC Instructions) secure memory technology. Known as the Codasip Prime platform, this innovative system facilitates the advanced development of CHERI memory-safe hardware and secure software using readily available IP. This platform empowers hardware and software engineers to assess and showcase the capabilities of the technology, create and execute software, and seamlessly integrate the hardware into broader test systems.

The significance of security in the business landscape is rapidly escalating, driven by recent regulations like the EU Cyber Resilience Act. Memory safety vulnerabilities are exploited in as many as 87% of cyberattack chains, underscoring the critical need for robust security measures.

• Codasip contributes SDK to open source initiatives
• Embedded RISC-V core tailored for automotive applications
• Introduction of the first RISC-V secure memory chip for embedded designs

Codasip views CHERI as a cost-effective solution for mitigating memory safety vulnerabilities. This technology, which is backward compatible, facilitates the transition to safer code through re-compilation. By rendering C/C++ memory safe, CHERI eliminates the need for expensive software rewrites, although it does necessitate new hardware.

The X730 64-bit core is implemented on an FPGA alongside specific IP for tag management for DDR memory, peripherals, and security IP for secure boot and secure debug functionalities like a True Random Number Generator and Test Access Port Protection Unit, as well as a debug probe.

Complementing the QEMU FPGA virtual platform, the Software Development Kit encompasses CHERI Linux, a C/C++ toolchain comprising a compiler and debugger, as well as secure boot capabilities.

“Our latest platform represents a game-changing advancement for consumer, automotive, and defense companies considering the adoption of CHERI,” remarked Jamie Broome, Chief Product Officer at Codasip. “Codasip Prime empowers software developers to design and assess their applications prior to chip fabrication. In addition to hardware IP and software, we provide expert engineering support from our CHERI specialists. By collaborating with the CHERI Alliance and RISC-V International, we ensure alignment with industry standards, enabling early adopters to have confidence in the future-proof nature of their integrations.”

Codasip is spearheading the standardization of a CHERI extension for RISC-V in partnership with other members of the CHERI Alliance. The X730 stands as the inaugural commercial implementation of the CHERI-RISC-V extension and is readily accessible to interested parties.