PCI-SIG announces PCIe 7.0 and optical interconnect revision for AI and data centres

The PCI-SIG has recently unveiled an updated version of its optical interconnect specification, aimed at boosting the performance of PCI Express (PCIe) technology. This revision also aligns with the PCIe 7.0 specification, which is designed to cater to the increasing bandwidth requirements of artificial intelligence (AI) at transfer rates of 128.0 GT/s.

The Optical Aware Retimer Engineering Change Notice (ECN) introduces modifications to the PCIe 6.4 specification and the latest PCIe 7.0 specification. It incorporates a PCIe timer-based solution, marking a significant milestone as the first standardized approach for implementing PCIe technology over optical fiber.

Al Yanes, President and Chairperson of PCI-SIG, emphasized the necessity for an industry-standard optical interconnect based on PCIe technology. He highlighted the introduction of the Optical Aware Retimer ECN as a crucial initial step towards integrating a modular optical solution. Yanes anticipates the primary adoption of this technology in data center applications such as AI/ML and cloud computing, with potential for diverse applications across various market segments as PCIe technology becomes more pervasive.

The PCIe retimer ECN seamlessly facilitates the integration of different optical technologies for optical interconnection between PCIe 6.4 and 7.0 specification-compliant silicon designs, including Switch, Root-Complex, and Endpoint components. These specifications offer enhanced reach across racks and pods, multiplexing capabilities, and data mapping across both electrical and optical domains. Additionally, they enable more space-efficient implementations compared to traditional electrical copper options.

The latest PCIe 7.0 specification is tailored to meet the demands of data-centric applications, encompassing AI/ML, 800G Ethernet, cloud services, and quantum computing. Concurrently, efforts are underway to pave the way for the PCIe 8.0 specification, ensuring continued support for industry investments and product roadmaps within the PCIe technology ecosystem.

With a raw bit rate of 128.0 GT/s and bidirectional speeds of up to 512 GB/s through an x16 configuration, the PCIe specification leverages PAM4 signaling and Flit-based encoding. This approach not only enhances power efficiency but also maintains compatibility with previous generations of PCIe technology. Al Yanes reiterated the enduring significance of PCIe technology as a high-bandwidth, low-latency IO interconnect, underscoring the tradition of doubling IO bandwidth every three years with the release of the PCIe 7.0 specification.