Rapidus signs 2nm deals with Synopsys, Cadence

 Rapidus in Japan has signed deals with both Synopsys and Cadence Design Systems for design tools for its 2nm foundry business and access to manufacturing data for AI.

Synopsys will have access to Rapdius manufacturing data for its AI tools, while Cadence will supply memory and interface IP optimised for backside power delivery.

The agreement with Synopsys will shorten design cycle time by natively modelling process sensitivity and variation in the design steps. This reduces the need for expensive re-characterization of libraries and memories during different phases of the process evolution leading to a significant reduction in design iterations and acceleration of the overall project execution cycle.

As part of the agreement, Synopsys will develop advanced design flows based on its AI-driven EDA suite and enable a broad IP portfolio on Rapidus’ 2nm gate-all-around (GAA) process. The collaboration will tap into the Rapidus Design for Manufacturing and Co-Optimization (DMCO) concept for simultaneously optimizing design and manufacturing and enabling agile design.

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Characterization of the IP library is one of the bottlenecks in semiconductor design cycle time because the IP needs to be recharacterized each time the process design kit (PDK) or manufacturing process is updated. It can take two to three months to generate a timing model, which drastically slows down the design process. 

The DMCO approach will use the Synopsys PrimeShield machine learning (ML)-based timing model generation tool employing sensitivity libraries whenever PDKs or manufacturing processes are updated. Additionally, calibration using silicon data from Rapidus’ short turnaround time (TAT) manufacturing process will improve model accuracy and accelerate design convergence.

By incorporating the concept of Manufacturing for Design (MFD) in addition to conventional Design for Manufacturing (DFM), Rapidus will be able to use sensors and AI in the wafer process to streamline designs based on silicon big data from the manufacturing process.

Synopsys will use this data in its AI-driven EDA flows alongside its interface and foundation IP for Rapidus process technologies to reduce integration risk and accelerate the path to silicon success.

“Our partnership with Synopsys is an important milestone in helping to simplify and quicken the design process. Rapidus’ vision for RUMS is to use a single-wafer front-end process. The massive amount of data that can be obtained from this process is highly compatible with Synopsys AI-driven EDA flows and IP, and we believe that this will be a step toward achieving our goal of short TAT production that is quicker than anywhere else,” said Dr. Atsuyoshi Koike, CEO of Rapidus.

Collaboration spans interface and memory IP utilizing 2nm gate-all-around, BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips

The collaboration with Cadence will support the Rapidus 2nm gate-all-around (GAA) process with backside power delivery network (BSPDN) technology to provide design solutions and IP portfolio to customers.

Rapidus and Cadence are working to develop an AI-driven digital and analog/mixed-signal reference design flow that includes Cadence design solutions. Customers will be able to use Cadence’s broad portfolio of interface and memory IP components, including HBM4, 224G SerDes, PCI Express 7.0 and more, while also taking advantage of 2nm GAA and BSPDN design and manufacturing solutions that support the DMCO concept.

“Our collaboration with Cadence on 2nm BSPDN technology puts us at the industry’s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we’re excited to set new technology standards and create transformative solutions for our mutual customers and the industry,” said Dr. Atsuyoshi Koike, CEO of Rapidus.

“Synopsys continues to play a mission-critical role as an on-ramp to the world’s leading foundries and we are often the first stop for foundry enablement,” said Sassine Ghazi, president and CEO of Synopsys. “Our extensive collaboration with Rapidus across Synopsys AI-driven EDA flows, IP and expert methodology services will facilitate an advanced DMCO solution that will enable designers to achieve optimal quality of results and high manufacturing yield for Rapidus’ 2nm GAA process.”