Synopsys and Siemens Digital Team Up for Intel Foundries 18A Process

Siemens Digital Industries Software has announced that its Calibre Platform tool for IC design verification and Analog FastSPICE (AFS) platform for analogue, RF, custom digital, and mixed-signal circuit verification have received certification for Intel 18A and Intel 16 process technologies. The 18A technology features a GAA transistor architecture and PowerVia backside power delivery, offering advanced capabilities for designers.

On the other hand, Siemens' Analog FastSPICE (AFS) platform has been certified for the Intel 16 technology, serving as a bridge to FinFET technology from planar nodes. The Intel 16 node provides RF and analogue capabilities, delivering 16nm class performance and low power consumption with simplified design rules and reduced mask requirements.

Meanwhile, Synopsys' digital and analogue EDA flows have been certified and optimized to meet power, performance, and area targets on the Intel 18A process, ensuring that designers can leverage the full potential of the technology for their projects.

In a strategic collaboration, Synopsys and Intel Foundry are working together on multi-die systems using Synopsys' 3DIC Compiler platform and Intel's foundry processes. This platform addresses the complex needs of Intel Foundry chip designers, offering automated routing for UCIe interfaces and enabling seamless co-design with Intel's EMIB packaging technology.

The Synopsys Multi-Die System Solution facilitates early architecture exploration, rapid software development, efficient die and package co-design, secure die-to-die connectivity, and enhanced manufacturing and reliability, providing a comprehensive solution for advanced system design.

Additionally, Siemens Digital Industries Software has joined forces with Intel Foundry to develop a comprehensive workflow for the foundry's embedded multi-die interconnect bridge (EMIB) approach, enabling high-density interconnect of heterogeneous chips within a package.

Through this collaboration, mutual customers can engage in early package assembly prototyping, hierarchical device floorplanning, co-design optimization, detailed implementation verification, signal and power integrity analysis, and Package Assembly Design Kit (PADK) driven assembly verification, streamlining the design process.

The Siemens technologies integrated into this reference flow include Xpedition™ Substrate Integrator software, Xpedition Package Designer software, Hyperlynx software SI/PI, and the Calibre nmPlatform tool, including Calibre 3DSTACK software, offering a comprehensive suite of tools for advanced chip design.