Synopsys Unveils PCIe 7.0 End-to-End IP Solution

Synopsys has recently unveiled a comprehensive suite of intellectual property (IP) tailored for end-to-end PCI Express 7.0 designs, which also includes the verification IP component.

The release of this IP coincides with the advancement of PCIe 7.0 to version 0.5, a significant milestone that aligns with Synopsys' tradition of introducing IP solutions for chip designers at this stage.

The IP portfolio for PCIe 7.0 encompasses the SERDES PHY physical layer, controller, encryption module, and verification IP, all poised to support the upcoming wave of chips expected to hit the market in the latter half of 2025.

According to Priyank Shukla, principal product manager for interface IP at Synopsys, "We have been involved in PCIe technology for 20 years, and with each iteration reaching version 0.5, we make the announcement. It's safe to say that our journey in designing this IP began two decades ago."

PCIe 7.0 introduces a doubling of bandwidth to 512Gbyte/s, but this enhancement also brings about increased power dissipation. Sectors like data centers and AI are anticipated to witness an 80% surge in power consumption, prompting a crucial emphasis on power reduction within the IP.

Shukla emphasized the importance of demonstrating silicon readiness as the standard progresses, stating, "The silicon must be validated by the time the standard hits 0.5. We showcased the PHY at 128Gbit/s last year, providing a tangible proof point for our capabilities."

Transitioning from PCIe 6.0 to 7.0 represents more of an incremental leap rather than a significant overhaul. Shukla noted, "From a controller perspective, minimal changes are anticipated. Being the sole IP company on the PCI-SIG board grants us insights into the evolving specification, enabling us to anticipate future developments."

As the standard solidifies and the ecosystem adapts, the focus shifts towards verification IP as the initial step in the design process. Designers are eyeing the first half of 2025 for tape out, aligning with the availability of design views, with the IP being offered in 5nm and 3nm nodes to cater to diverse customer requirements.

Addressing the diverse needs of the ecosystem, Shukla highlighted, "We cater to a wide spectrum of optimizations as customers pursue various approaches, from chiplet development to monolithic devices."

Furthermore, the PHY component of PCIe 7.0 holds versatility beyond PCIe, extending its utility to specifications like CXL for distributed memory and UCIe for chiplet interconnectivity.

Shukla underscored the ongoing efforts to enhance power efficiency, building on the progress made with previous IP generations. "We are achieving a 50% improvement in power efficiency across all layers. For instance, the optimization of logic within the controller has led to reduced gate count," he explained.

PCIe 7.0 incorporates features such as RAS-DES from PCIe 6.0, leveraging Synopsys' extensive experience with over 75 licenses to streamline debugging processes. Additionally, it integrates ARM confidential computing (CCA) and AES-GCM packet encryption to meet FIPS 140-3 certification standards.

For more information, visit www.synopsys.com.