Cutting-Edge 2nm Gate-All-Around ICs Get Boost with Training-Grade PDK

Imec, the Belgian semiconductor research lab, has recently launched an early-access process design kit (PDK) for the N2 (2nm ICs) node. This PDK will enable virtual digital designs in imec's N2 technology, including backside power delivery network. According to imec, this development will provide academia and industry with the necessary tools to train future semiconductor experts and facilitate the transition of products into next-generation technologies through meaningful design pathfinding.

The PDK is intended to be embedded in EDA (Electronic Design Automation) tool suites, such as those offered by Cadence Design Systems and Synopsys. Additionally, imec is offering a concomitant training program through EuroPractice, which is scheduled to begin early in Q2. This hands-on training will utilize Cadence and Synopsys software, further enhancing the learning experience.

Imec has explained how their pathfinding kit differs from normal PDKs. Foundry PDKs typically provide chip designers with access to a library of tested and proven components, ensuring functional and reliable designs. However, these PDKs are usually made available to the ecosystem once the technology reaches a critical level of manufacturability. The restricted access and the need for non-disclosure agreements (NDAs) have created a high threshold for academia and industry to access advanced technology nodes during their development. By providing access to the imec N2 PDK, both academia and commercial companies will benefit from increased accessibility to advanced technology nodes.

The N2 PDK includes infrastructure for digital design, which is based on a set of digital standard cell libraries and SRAM IP macros. Imec also has plans to extend the pathfinding platform to more advanced nodes, such as A14.