Renesas Explores Few-Pin RISC-V MCUs

Resasas has introduced its in-house developed 32-bit RISC-V core into a new series of general-purpose MCUs, marking a significant milestone following its previous RISC-V projects with Anders and SiFive.

Initially announced in November, the core implementation boasts the ability to support various standard RISC-V options, complemented by Renesas' own enhancements. These include a stack monitor register designed to safeguard against malicious software, a dynamic branch prediction unit to enhance average execution throughput, and a context-saving register bank for accelerated interrupt response.

For low pin-count packages, a two-wire compact JTAG debug feature can be integrated, along with performance monitor registers for benchmarking purposes and an instruction tracing unit. The new microcontrollers, known as the R9A02G021 group, are available in packages ranging from 16 to 48 pads, including 16-pad WLCSP and QFNs with 24, 32, or 48 pads in sizes from 4 x 4 to 7 x 7mm.

These MCUs are based on the RV32I instruction set and incorporate two-wire JTAG and Renesas' core-local interrupt controller (CLIC). Operating at speeds of up to 48MHz, they deliver an impressive 3.27 Coremark/MHz performance, with power consumption rated at 162µA/MHz or 300nA in stand-by mode with a 4μs wake time. The devices support a voltage range of 1.6 to 5.5V and operate within a temperature range of -40 to 125°C.

Featuring 128kbyte of instruction flash, 4kbyte of data flash, and 16kbyte of RAM, these MCUs also include a 12-bit ADC, an 8-bit DAC, and various serial communication interfaces such as UART, SPI, and I2C. Renesas has incorporated its 'SAU' peripheral to enable the implementation of up to six simplified SPI interfaces, additional UARTs, or simplified I2C interfaces, depending on the package size.