RED Unveils VISC Technology

RED Semiconductor (“RED”) has made a groundbreaking announcement with the introduction of VISC, an innovative algorithmic microprocessor ISA and hardware design that pushes the boundaries of RISC-V for Edge AI, autonomy, and cryptography.

VISC stands out as an accelerated RISC-V microprocessor core that excels in optimizing complex mathematical algorithms for parallel execution within its reconfiguration hardware engine. The performance enhancement offered by VISC, when compared to standard RISC-V, is particularly sought after in the current era of ubiquitous AI and the exponential growth of data.

The VISC ISA empowers developers to articulate intricate algorithms using significantly less code than what would be required with the standard RISC-V instruction set, RISC-V vector extensions, or other ISAs like x86 and Arm. Through its hardware, VISC efficiently decompresses entire algorithms and orchestrates the execution of elements for optimized parallel processing.

When combined, the VISC ISA and hardware have the potential to deliver over a 100x increase in algorithmic performance per unit of power consumed. Its Single-Issue Multi-Execute (SiMex™) architecture further fine-tunes performance for silicon area efficiency.

“RISC-V has the potential to emerge as the preferred architecture for ubiquitous edge AI, akin to how Arm established itself as the architecture for smartphones,” remarked RED Semiconductor CEO, James Lewis. He added, “To achieve this, a distinctive and potent hardware approach is essential for executing AI calculations with superior efficiency."

RED is leading the charge with VISC, a RISC-V-based solution that revolutionizes algorithmic processing to deliver faster, more compact, and energy-efficient edge AI solutions. VISC combines the performance advantages of dedicated hardware accelerators with the versatility of a general-purpose microprocessor, enabling SoC developers to accomplish multiple heterogeneous compute functions using a unified instruction set and hardware core.

“RED Semiconductor could potentially play a pivotal role in the RISC-V community by introducing VISC at a crucial juncture when the technology is gaining momentum,” noted Jon Peddie, president of Jon Peddie Research. He emphasized, “VISC has the capability to reshape heterogenous SoC design for sectors like edge AI, similar to how GPUs transformed the smartphone market, thereby creating substantial value."

The VISC execution architecture is designed as a fully functional standalone RISC-V compatible core, ideal for integration into ASICs and FPGAs. It boasts exceptional memory efficiency, eliminating memory accesses during computation to enhance security. Its versatility in running general-purpose compute functions, operating systems, mathematical acceleration, signal processing, and graphics functions positions it as a valuable co-processor or primary processor in heterogenous computing SoCs.

RED’s approach to algorithmic processing for RISC-V leverages a precoding system that enables parallelization of RISC-V scalar instructions. VISC's registers, decoders, and execution engine are finely tuned for efficient parallel computation of complex repetitive functions such as FFT, DCT, Matrix Multiplication, and Big Integer Maths. Enhancing the efficiency of these functions exponentially is crucial for enabling widespread and secure AI computation.

A RISC-V processor equipped with VISC can efficiently handle large datasets, facilitating data-intensive applications like AI inferencing, high-performance computing, real-time analytics, and video streaming.

VISC delivers a 100x code densification, execution performance boost, and power reduction. Additionally, it boasts remarkable code density – for instance, a matrix multiplication operation requires only three instructions, a stark contrast to the 100+ instructions needed by mainstream ISAs today. VISC's scalability from one to over 1,000 cores caters to a broad spectrum of applications ranging from edge to HPC hyperscale scenarios. While currently implemented for RISC-V, VISC is fundamentally ISA agnostic, leaving the door open for potential application to other instruction set architectures in the future.

The VISC architecture represents a significant leap in execution performance. It features a Decompression Engine that concurrently decodes code and accelerates issue to execution units, enabling multi-execution from a single-issue pipeline. Subsequently, an Execution Optimization Engine meticulously sequences and executes up to 16 parallel instructions. VISC's Versatile Deep Register Set, accessible by all instruction types, facilitates the execution of complex routines in registers, minimizing cache misses and keeping all processing within the core until the routine is completed, thereby reducing potential security vulnerabilities.

“Market predictions from SHD Group suggest that by 2030, 16 billion SoCs will incorporate RISC-V cores,” Lewis highlighted. He expressed confidence in this projection, emphasizing the need for differentiation in performance, security, and design methodology. RED Semiconductor is actively forging partnerships with RISC-V, cryptography, and tools companies to deliver a compelling solution that can transform a RISC-V processor design into an AI powerhouse.

VISC opens up possibilities for processors across various markets where algorithmic processing is increasingly essential, including aerospace, AI/ML, AR/VR, autonomy, critical infrastructure, fintech, healthtech, high-performance computing, and industry 4.0.

RED Semiconductor is a proud member of the inaugural cohort of ChipStart UK, a government-backed incubator launched under the National Semiconductor Strategy and managed by Silicon Catalyst UK.