SiTime, a leading company based in the US, has recently introduced a groundbreaking family of MEMS clock system-on-a-chip designed specifically for data centre applications. Known as the Chorus family, these clock generators are tailored for precision AI datacentre timing applications, offering a significant advancement in performance and size reduction compared to traditional standalone oscillators and clocks.
The innovative MEMS-based clock-system-on-a-chip (ClkSoC) family, encapsulated in a compact 4 x 4mm QFN chip, integrates clock, oscillator, and resonator technologies. This integration not only simplifies system clock architecture but also accelerates design time by up to six weeks, providing a more efficient solution for data centre timing requirements.
Featuring an impressive RMS phase jitter of 70fs from 12 kHz to 20 MHz, the chip offers programmable frequency ranging from 1 MHz to 700 MHz with stability of ±20 ppm and ±50 ppm across a wide temperature range from -40°C to 105°C. Additionally, it provides up to four differential (LVPECL, LVDS, LPHCSL) or eight LVCMOS outputs and programmable power rails of 1.8V, 2.5V, or 3.3V, catering to diverse application needs.
With the increasing demand for rapid upgrade cycles in AI hardware to support data and compute-intensive workloads, precise timing becomes crucial. The Chorus MEMS clocks, when combined with timing products from Aura Semiconductor, offer a comprehensive solution to meet these evolving requirements, ensuring optimal performance and efficiency in data centre operations.
According to Piyush Sevalia, the executive vice president of marketing at SiTime, "AI is propelling the need for higher data throughput and lower power consumption in data centres." He further explains, "Chorus eliminates the need for discrete clock components like oscillators and resonators, providing integrated clock generators that enhance performance and efficiency. This exemplifies our commitment to revolutionizing the timing market."
The integrated MEMS resonator in the Chorus family overcomes the limitations of traditional clock generators by addressing issues such as noise and impedance matching. By replacing up to four standalone oscillators, Chorus can reduce the board area for timing by up to 50% in various data centre equipment, including servers, switches, acceleration cards, and network interface cards, thereby optimizing space utilization and enhancing overall system performance.
Moreover, the configurable spread-spectrum clock generation in the Chorus chip helps mitigate EMI concerns, ensuring compliance with PCI Express standards from version 1 to 6. SiTime is currently offering sampling of the Chorus family to strategic customers, with general sampling availability expected in the second half of 2024, marking a significant milestone in advancing data centre timing technology.
For more information about SiTime and the Chorus family of clock generators, visit www.sitime.com.