Synopsys Collaborates with TSMC on 2nm Analog IP and Photonics

Synopsys and TSMC have joined forces to develop an end-to-end electronic and silicon photonics reference flow while also working on analog IP for TSMC’s cutting-edge 2nm process technology. This collaboration aims to push the boundaries of chip design and enable the creation of innovative solutions for various industries.

The development of new Foundation and Interface IP on the 2nm N2P process is currently underway, following the success of silicon-proven IP on N3P. Already, the first digital chips for artificial intelligence (AI) have been successfully taped out at TSMC using the 2nm technology, showcasing the progress made in advancing semiconductor manufacturing.

Both digital and analog design flows have received certification on TSMC N3P and N2 process technologies, with deployment in AI, high-performance computing, and mobile designs by various companies. The utilization of the Synopsys.ai EDA suite on the TSMC N3/N3P and N2 nodes has been instrumental in achieving these milestones.

The PHY IP offerings on N2 and N2P include a wide range of interfaces such as UCIe, HBM4/3e, PCIe, MIPI, USB, and DDR5, catering to diverse design requirements. Similarly, the Foundation and Interface IP for N3P cover essential components like Ethernet, MIPI, USB, LPDDR, and PCIe, with ongoing development for DDR5 MR-DIMM.

A notable addition to Synopsys’ capabilities is the new flow for TSMC N5 to N3E migration, complementing existing flows for N4P to N3E and N3E to N2 processes. This enhancement, along with interoperable process design kits and physical verification runsets, streamlines the transition of designs to TSMC's advanced process technologies.