Synopsys Collaborates with TSMC on 2nm Analog IP and Photonics

Synopsys and TSMC are working together to develop an end-to-end electronic and silicon photonics reference flow, in addition to creating analog IP on TSMC’s cutting-edge 2nm process technology. This collaboration marks a significant milestone in the semiconductor industry, showcasing the commitment to innovation and pushing the boundaries of what is possible in chip design.

The development of new Foundation and Interface IP on the 2nm N2P process is currently underway, following the successful implementation of silicon-proven IP on N3P. Notably, the first digital chips for artificial intelligence (AI) have already been taped out at TSMC using the 2nm process, demonstrating the rapid progress being made in advancing semiconductor technology.

Furthermore, the digital and analog design flows have received certification on TSMC N3P and N2 process technologies, with deployment in various sectors such as AI, high-performance computing, and mobile designs. The utilization of Synopsys.ai EDA suite on the TSMC N3/N3P and N2 nodes has enabled companies to streamline their design processes and achieve enhanced performance in their products.

The PHY IP offerings on N2 and N2P encompass a wide range of interfaces including UCIe, HBM4/3e, PCIe 7.x/6.x, MIPI C/D-PHY and M-PHY, USB, DDR5 MR-DIMM, and LPDDR6/5x. Similarly, the Foundation and Interface IP for N3P feature essential components like 224G Ethernet, UCIe, MIPI C/D-PHY and M-PHY, USB/DisplayPort, eUSB2, LPDDR5x, DDR5, and PCIe 6.x, with ongoing development for DDR5 MR-DIMM.

A notable addition to Synopsys’ offerings is the new flow designed for TSMC N5 to N3E migration, complementing the existing flows for N4P to N3E and N3E to N2 processes. This expansion provides design teams with the tools and resources needed to efficiently transition their designs to TSMC's advanced process technologies, ensuring seamless integration and optimal performance.

The collaboration between Synopsys and TSMC extends to the development of the TSMC Compact Universal Photonic Engine (COUPE) technology, aimed at addressing the demand for low-latency, power-efficient, and high-bandwidth solutions for AI and multi-die designs. By leveraging SoIC-X chip stacking technology, COUPE offers enhanced energy efficiency and reduced impedance, paving the way for future advancements in chip design and packaging.