SiPearl postpones release of Rhea1 supercomputer chip to 2025

European supercomputer chip designer SiPearl has announced a further delay in the release of its highly anticipated Rhea1 chip. Originally scheduled for completion by the end of 2022, the company is now aiming to have the first samples of the Rhea1 supercomputer chip available in 2025.

SiPearl has revealed that the Rhea1 chip will be equipped with 80 ARM Neoverse V1 cores, each featuring two Scalable Vector Extension (SVE) units of 256 bits per core. Additionally, the chip will include the ARM Neoverse CMN-700 Coherent Mesh Network on Chip (NoC) and built-in High Bandwidth Memory with 4 stacks of HBM and four DDR5 interfaces to efficiently handle memory-bound AI frameworks like transformers.

The delay in the Rhea1 chip release comes as a setback for SiPearl, as the company had initially planned to tape out the chip in early 2024 with sampling expected later that year for the Jupiter supercomputer center in Germany. Despite the setback, Rhea1 is poised to be supported by a wide range of compilers, libraries, and tools, catering to both traditional programming languages such as C/C++, GO, and RUST, as well as modern AI frameworks like TensorFlow and PyTorch.

SiPearl's CEO and founder, Philippe Notton, expressed confidence in the capabilities of the Rhea1 chip, stating, “Combining the performance and energy-efficiency of ARM Neoverse V1 cores with in-package HBM and embedding SiPearl patented memory and power management schemes, Rhea1 will fulfill the mission entrusted by EuroHPC JU and the European Processor Initiative consortium."

However, the latest advancements in AI chip technology are moving towards the utilization of V3 Neoverse cores and HBM 2e memories, indicating a potential challenge for SiPearl in maintaining competitiveness in the rapidly evolving market.

With over 190 employees spread across locations in France, Germany, and Spain, SiPearl is expanding its operational footprint by establishing a subsidiary in Bologna, Italy. This strategic move aligns with the company's collaboration with Cineca, the largest Italian supercomputing center and a key partner in the European Processor Initiative (EPI) consortium.

The ongoing collaboration between SiPearl and the EPI project aims to define the hardware Common Platform for the chip and system integration, focusing on technologies that enable the design of decoupled systems combining hybrid compute units or chiplets. This initiative will explore interfaces such as CXL, CCIX, and PCIe, as well as analyze die-to-die interfaces for chiplet-chiplet interconnects like bunch of wires (BOW), UCIe, and XSR.

For more information about SiPearl and the Rhea1 chip, visit www.sipearl.com.