Intel and TSMC to Unveil 2nm Processes at IEDM

In a recent publication, researchers at TSMC are gearing up to reveal the innovative N2 manufacturing process, a groundbreaking nominal 2nm process specifically tailored for applications in AI, mobile devices, and high-performance computing. Concurrently, during the same session, engineers from Intel will delve into the intricacies of scaling RibbonFETs, the proprietary nanosheet transistors developed by Intel.

Anticipated presentations at the upcoming IEDM conference suggest that the N2 process by TSMC could potentially deliver a remarkable 15 percent increase in speed or a 30 percent reduction in power consumption, all while enhancing chip density by at least 15 percent compared to its predecessor, the N3 (3nm nominal) process introduced in 2022.

The cross-sectional view of the N2 interconnect stack, showcasing the copper redistribution layer, underscores the seamless integration of the N2 platform with advanced 3D technologies. This integration is expected to play a pivotal role in enhancing the overall performance and efficiency of semiconductor devices.

Furthermore, a paper titled "2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC, and Mobile SoC Applications," authored by G. Yeap et al. from TSMC, is poised to unveil an SRAM macro boasting a world-record density of 38Mbits per square millimeter.

Additionally, the paper will shed light on the middle- and back-end-of-line interconnect technologies, featuring a scalable copper-based redistribution layer for flexible placement of input/output pads, a flat passivation layer for enhanced reliability, and through-silicon vias (TSVs) for interconnecting devices across different layers. The researchers have expressed confidence in the N2 platform meeting wafer-level reliability standards, with full qualification expected by 2025 and mass production slated for 2026.

On a parallel front, in a paper titled "Silicon RibbonFET CMOS at 6nm Gate Length," A. Agrawal et al. from Intel will showcase the development of nanosheet technology (RibbonFETs) featuring 6nm gates and a 45nm contacted polysilicon pitch (CPP) without compromising electron mobility.