Keysight adds UCIe, BoW standards to Chiplet PHY Designer 2025

Keysight Technologies has added support for both interconnect standards to the latest version of its Chiplet PHY Designer 2025 design tool.

The enhanced software introduces simulation capabilities for the Universal Chiplet Interconnect Expressä (UCIe) 2.0 standard and the Open Computer Project Bunch of Wires (BoW) standard.

Chiplet PHY Designer enables pre-silicon level validation of the die to die (D2) interconnect, streamlining the path to tapeout.

 As AI and data centre chips grow more complex, ensuring reliable communication between chiplets becomes crucial for performance. UCIe and BoW define the interconnects between chiplets within an advanced 2.5D/3D or laminate/advanced package. By adopting these standards and verifying chiplets for compliance, designers contribute to the growing ecosystem for chiplet interoperability, reducing costs and risks in semiconductor development.

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The tool verifies that designs meet UCIe 2.0 and BoW standards, enabling seamless integration across advanced packaging ecosystems. It also automates simulation and compliance testing setup, such as Voltage Transfer Function (VTF), simplifying chiplet design workflows.

Support for advanced clocking scheme analysis, such as quarter-rate data rate (QDR), supports precise synchronisation in high-speed interconnects.

“Keysight EDA launched Chiplet PHY Designer one year ago as the industry’s first pre-silicon validation tool to provide in-depth modelling and simulation capabilities; this enabled chiplet designers to rapidly and accurately verify that their designs meet specifications before tapeout,” said Hee-Soo Lee, High-Speed Digital Segment Lead, Keysight EDA.

“The latest release keeps pace with evolving standards like UCIe 2.0 and BoW while delivering new features, such as the QDR clocking scheme and systematic crosstalk analysis for single-ended buses. Engineers using Chiplet PHY Designer save time and avoid costly rework, ensuring their designs meet performance requirements before manufacturing. Early adopters, like Alphawave Semi, attest that Chiplet PHY Designer ensures seamless operation and interoperability for 2.5D/3D solutions available to their chiplet customers.”

Keysight is set to acquire photonics design tools from Synopsys and and a power analysis tool from Ansys to allow their $35bn merger to go ahead.