SureCore IP Reduces Power Consumption for AI Chips at KU Leuven

KU Leuven in Belgium has implemented innovative IP technology from SureCore to significantly reduce dynamic power consumption in an AI chip by an impressive 40%. The PowerMiser IP, integrated into a 16nm FinFET process, has demonstrated the capability to slash dynamic power usage by up to 50% and static/leakage power by up to 20% when compared to conventional SRAM solutions offered by foundries and other providers. These efficiency gains are realized across the entire spectrum of process variations, voltage levels, and operating temperatures. SureCore, based in Sheffield, UK, is now gearing up to introduce a 7nm variant of this groundbreaking technology.

One of the key strengths of SureCore lies in its ability to optimize AI memory IP specifically for low power consumption, making it an ideal choice for cutting-edge applications in the semiconductor industry. The company's low power memory compiler tailored for 16nm FINFET designs has garnered significant attention for its ability to deliver superior performance while keeping power demands in check.

Paul Wells, the CEO of SureCore, emphasized the evolution of the 16nm node from its origins in mobile and high-performance computing solutions to its current status as a mature platform with widespread adoption. He highlighted the shift in focus towards leveraging the node's enhanced density, reduced leakage, and improved power characteristics for emerging technologies such as wearables, medical devices, and Edge-AI applications. Wells underscored the pivotal role played by SureCore's PowerMiser SRAM in enabling developers to meet stringent power efficiency targets in these cutting-edge applications.

Professor Wim Dehaene from KU Leuven shared insights into the university's collaboration with SureCore, citing the integration of PowerMiser IP into a novel neural processing accelerator chip designed for AI workloads. The chip, tailored to handle intensive computational tasks, presented significant power consumption challenges that were effectively addressed through the use of SureCore's innovative technology. Professor Dehaene, affiliated with the MICAS research division within KU Leuven's electrical engineering department, highlighted the successful development of a digital in-memory computing (DIMC) solution for vision recognition, leveraging substantial amounts of SRAM memory.

The HUNBN 16nm FinFET chip, showcasing a complete IMC-based accelerator, demonstrated the energy-efficient nature of DIMC as a viable alternative to traditional accelerators, particularly for moderately sized models that can be accommodated on the chip. This breakthrough resulted in the creation of a neural network chip boasting an impressive efficiency of 24 TOPS/W at 4-bit quantization and delivering a performance of 30 frames per second. The integration of AI techniques has further heightened the importance of addressing power consumption challenges in IoT applications, with the advanced logic and memory designs developed by MICAS poised to play a crucial role in enabling a smarter, safer, and more sustainable society.