The semiconductor industry is constantly evolving, with companies like Applied Materials leading the way in developing innovative solutions to enhance chip performance. Recently, Applied Materials introduced an enhanced low-k dielectric material aimed at reducing chip wiring capacitance and strengthening logic and DRAM chips for 3D stacking.
Low-k dielectrics and copper have long been staples in integrated circuits (ICs). However, with monolithic integration moving towards smaller dimensions, the challenge lies in ensuring the mechanical strength of chips and minimizing electrical resistance. Thinner dielectric materials can make chips mechanically weaker, while narrowing copper wires can lead to significant increases in electrical resistance and power consumption.
Applied Materials has been at the forefront of addressing these challenges. In the past, the company utilized its Black Diamond material to surround copper wires with a low-dielectric-constant film. The latest advancement in this material, known as Black Diamond PECVD [Plasma-Enhanced Chemical Vapor Deposition], not only reduces the minimum k value but also enhances mechanical strength, enabling logic and memory die stacking.
Moreover, Applied Materials has officially unveiled its latest liner-barrier materials system, which is already in use at the 3nm node. This system features a binary metal combination of ruthenium and cobalt (RuCo), reducing the thickness of the wiring liner by 33 percent to 2nm. Additionally, it improves surface properties for void-free copper reflow and decreases electrical line resistance by up to 25 percent, ultimately enhancing chip performance and reducing power consumption.
Prabu Raja, president of the Semiconductor Products Group at Applied Materials, emphasized the importance of energy-efficient computing in the AI era. He stated, "Applied's newest integrated materials solution allows the industry to scale low-resistance copper wiring to the emerging angstrom nodes. Simultaneously, our latest low-k dielectric material reduces capacitance and strengthens chips, paving the way for new heights in 3D stacking."