New Accelerated RISC-V Core: Edge AI and Cryptography Optimized

Red Semiconductor has made waves in the tech industry with the announcement of RISC-V instruction set extensions and a groundbreaking hardware design tailored for edge AI and cryptography applications in ASICs and FPGAs.

The hardware, dubbed 'VISC', represents an accelerated RISC-V core that excels in optimizing complex mathematical algorithms for parallel execution within its reconfiguration hardware engine. Red Semiconductor boasts that the VISC ISA enables developers to succinctly describe intricate algorithms using significantly less code compared to the standard RISC-V instruction set, RISC-V vector extensions, or other ISAs like x86 and Arm.

"Our instructions efficiently vectorize RISC-V's standard scalar instructions to facilitate VISC's parallel execution sequencing," explained a representative from Red Semiconductor. "This approach proves to be more streamlined than utilizing RISC-V's own RVV instructions and vector registers."

Described as 'single-issue multi-execute' hardware, VISC leverages precoding to parallelize RISC-V scalar instructions. The architecture's registers, decoders, and execution engine are meticulously optimized for parallel computation of functions such as FFT (fast Fourier transform), DCT (discrete cosine transform), matrix multiplication, and 'big integer' mathematics, ensuring precise results from long number arithmetic as opposed to floating-point approximations.

For FFT computations, Red Semiconductor disclosed to Electronics Weekly that their architecture condenses over 2,000 instructions from other ISAs into a mere 8-12 instructions. Similarly, for DCT, the reduction is from >2,000 instructions to 24-30 instructions, and for 'positional popcount' big data analysis, the reduction is from >500 instructions to 10-14 instructions.

"In each scenario, the reduction is achieved through a combination of VISC's set-up instructions configuring the hardware for optimal execution sequences and the 'maths toolbox' instructions that introduce new instruction forms layered atop the basic RISC-V instructions," shared Red Semiconductor, withholding specifics on the hardware reconfiguration process and the instructions utilized in the aforementioned examples.

Scalability across different implementations is achieved by adjusting the number of execute pathways per instruction pipeline, the number of instruction pipelines per VISC core, or the number of VISC cores. Red Semiconductor indicated that initial VISC core variants will prioritize scalability of execution pathways, with plans for instruction pipeline and core scaling in subsequent stages of the roadmap.

RED Semiconductor proudly stands as a member of the inaugural cohort of the UK Government-backed ChipStart incubator, a program initiated through the National Semiconductor Strategy and managed by Silicon Catalyst UK.