Quantum Chip Achieves Cryogenic Milestone

A groundbreaking achievement in the field of quantum computing has been reached with the successful tape-out of a demonstrator chip designed to operate at cryogenic temperatures in the UK.

The cryogenic chip is the result of a collaborative effort within a UK project involving key players such as SureCore, Agile Analog, and the University of Glasgow. The project, titled “Development of CryoCMOS to Enable the Next Generation of Scalable Quantum Computers,” aims to validate cryogenic SPICE models and intellectual property for control and measurement ASICs to be integrated within the cryostat alongside the quantum processor.

One of the main challenges addressed by the project is the need to move control electronics inside the cryostat to reduce latency and cabling. This shift requires the electronics to function at extremely low temperatures, reaching as low as 4 Kelvin, which is a critical aspect of the project's objectives.

Paul Wells, CEO of SureCore, expressed his optimism about the project's impact, stating, “This project will enable the UK to be seen as a center of excellence not only for Quantum Computing but also for cryogenic transistor modeling as well as cryogenic IP and chip design.” The successful integration of cryogenic IPs by Agile Analog's physical design team marks a significant milestone in the development of the control chip.

Building on the success of a previous test chip for cryogenic memory, Barry Paterson, CEO of Agile Analog, highlighted the importance of gaining experience and knowledge in silicon performance at such challenging cryogenic temperatures. This experience is expected to drive future IP developments in the Quantum computing domain.

SureCore's expertise in ultra-low power memory design has been instrumental in creating embedded Static Random Access Memory (SRAM) capable of operating at near absolute zero temperatures required by Quantum Computers. By re-characterizing standard cell and IO cell libraries for cryogenic operation, an industry-standard physical design flow can be readily adopted, facilitating the development of cryogenic SoCs.

The integration of control electronics close to qubits within the cryostat is crucial for scaling Quantum Computing. Current designs face limitations due to the operating characteristics of transistors at cryogenic temperatures. By developing interface chips that can control and monitor qubits at these extreme conditions, the potential for significant advancements in Quantum Computing is evident.

Traditionally, room temperature control electronics are connected to cryostat-housed qubits via bulky cabling. The ability to create custom cryogenic control SoCs that can be colocated with qubits inside the cryostat will not only reduce costs and size but also minimize latency, offering a promising path for Quantum Computing scaling.

The project's ultimate goal is to provide a suite of foundation IP that can be licensed to designers, empowering them to accelerate their Cryo-CMOS SoC designs. The next phase involves characterizing the demonstrator chip at cryogenic temperatures to further enhance performance and validate the models for future advancements in Quantum Computing.

For more information, visit www.sure-core.com.