World’s largest FPGA boosts Synopsys prototyping, emulation systems

Synopsys has used the world’s largest FPGA, the AMD Versal Premium VP1902 adaptive SoC, to double the capacity and speed of its prototyping and emulation systems.

The HAPS-200 prototyping system can run chip designs with up to 10.8bn gates at the RTL level long before silicon is ready, while the ZeBu-200 emulation system supports up to 15.4bn gates to run applications on virtual models of the chip.

A new hardware architecture called Emulation and Prototyping Ready (EP-Ready) which links six of the AMD FPGA devices in the hardware. This architecture also support the use of both the HAPS and ZeBu systems for emulation and prototyping within and across multiple projects to mix RTL code and virtual models in a hybrid digital twin. 

Multi-threading support also now allows that hybrid system to boot an operating system such as Android in less than 10 minutes on a full chip design, allowing application software to be tested.

These systems are being used by chip designers Nvidia, ARM, AMD and SiFive to test out both the silicon design at up to 50MHz but also the software that runs on the chips.

“With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions,” said Narendra Konda, vice president, Hardware Engineering at Nvidia. 

“The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are aiming to scale our HAPS-200 deployment to take full advantage for our software development teams.” 

The use of the Versal Premium VP1902, launched back in 2023, has allowed a 4x improvement in debug performance in the HAPS-200 and doubling of the emulation speed in the ZeBu-200. The SOCs double the FPGA gates of the previous generation with up to 18.5M logic cells, as well as twice the I/O bandwidth at 2.3Gbit/s for chip-to-chip interfacing and 2.3x the transceiver bandwidth with 112G PAM-4 modulation for high speed PCIExpress Gen5.0 links between the boards.

There are also two ARM Cortexc-A72 processors for applications processing and two ARM Cortex-R5F cores for real time processing.

The debug performance stems from improvements in several areas, says Frank Schirrmeister, Executive Director of Product Management and System Solutions at Synopsys.

Improved system integration of the FPGAs, allowing data storage in trace buffers,  and the system design provides a faster connection between the HAPS-200 and ZeBU-200 hardware and the host server where the debugging takes place. There are also software improvements in ZeBu Software and HAPS Protocompiler that handle the debug data with Synopsys Verdi running on the host server. 

“The 2x speedup in the ZeBu-200 stems from a combination of the AMD VP1902‘s capacity, our system integration, and our software,” he said.

Users can map larger portions of designs into the VP1902, which reduces the communication across pins that would be required if splitting the same design portion into smaller FPGAs of the previous generation.   

The ZeBu Software and HAPS Protocompiler also optimize the mapping of a user’s design portions into the FPGAs in a way that is optimized for communication and performance, given the cabling and configuration of the systems.   

“With the industry approaching 100s of billions of gates per chip and 100s of millions of lines of software code in SoC and multi-die solutions, verification of advanced designs poses never-before seen challenges,” said Ravi Subramanian, chief product management officer, Synopsys. “Continuing our strong partnership with AMD, our new systems deliver the highest HAV performance while offering the ultimate flexibility between prototyping and emulation use. Industry leaders are adopting Synopsys EP-Ready Hardware platforms for silicon to system verification and validation.”