4096-Spin Annealing Processor Boosts Problem-Solving

Researchers at the Tokyo University of Science have made a groundbreaking advancement in the field of quantum computing by designing a scalable, fully-coupled annealing processor with 4096 spins. This innovative processor boasts parallelized capabilities that significantly accelerate problem-solving processes, marking a significant leap forward in the realm of combinatorial optimization.

Annealing processors are specifically tailored to tackle combinatorial optimization problems, where the primary objective is to identify the optimal solution from a finite set of possibilities. The complexity of these problems necessitates the use of fully coupled components in the processors, a requirement that directly impacts their scalability.

Under the leadership of Professor Takayuki Kawahara, a team of researchers at the Tokyo University of Science successfully developed and tested a scalable annealing processor that integrates 4096 spins on a single board, utilizing 36 CMOS chips. This achievement represents a major milestone in the quest for advanced information processing capabilities at the edge, rather than relying solely on cloud-based solutions.

The newly developed processor incorporates two cutting-edge technologies pioneered at the Tokyo University of Science. The first is the "spin thread method," which enables 8 parallel solution searches, while the second technique reduces chip requirements by approximately half compared to traditional methods. Operating at a modest 10MHz with a power consumption of 2.9W (1.3W for the core part), the processor demonstrated its efficiency by solving a vertex cover problem with 4096 vertices.

In terms of power performance ratio, the processor outperformed simulations of a fully coupled Ising system on a standard PC (i7, 3.6GHz) using annealing emulation by an impressive 2,306 times. Furthermore, it surpassed the core CPU and arithmetic chip by 2,186 times, underscoring its remarkable computational capabilities.

Looking ahead, Professor Kawahara envisions further advancements in this technology, aiming to collaborate on a joint research initiative to develop an LSI system with computing power equivalent to a 2050-level quantum computer for solving combinatorial optimization problems. The ultimate goal is to achieve this feat without the need for air conditioning, large equipment, or cloud infrastructure, leveraging existing semiconductor processes. By 2030, the team aims to scale up to 2 million spins and explore the potential for creating new digital industries based on this groundbreaking technology.