Optimised Edge AI and Cryptography with Accelerated RISC-V Core

Red Semiconductor has recently unveiled groundbreaking RISC-V instruction set extensions and a hardware design tailored for edge AI and cryptography applications in ASICs and FPGAs.

The newly introduced hardware, named 'VISC', features an accelerated RISC-V core that excels in optimizing complex mathematical algorithms for parallel execution within its reconfiguration hardware engine. Red Semiconductor asserts that the VISC ISA (instruction set architecture) empowers developers to succinctly describe intricate algorithms using significantly less code compared to the standard RISC-V instruction set, RISC-V vector extensions, or other ISAs such as x86 and Arm.

Red elaborated on the innovation, stating, "Our instructions efficiently vectorize RISC-V's standard scalar instructions to facilitate VISC's parallel execution sequencing. This approach proves to be more streamlined than utilizing RISC-V's RVV (vector) instructions and vector registers."

Described as 'single-issue multi-execute' hardware, VISC leverages precoding to parallelize RISC-V scalar instructions. The company has optimized registers, decoders, and the execution engine for parallel computation of functions like FFT (fast Fourier transform), DCT (discrete cosine transform), matrix multiplication, and 'big integer' mathematics, ensuring precise results from long number arithmetic as opposed to floating-point approximations.

For FFT, Red Semiconductor claims a reduction from over 2,000 instructions in other ISAs to merely 8-12 instructions with its architecture. Similarly, for DCT, the reduction is from over 2,000 instructions to 24-30 instructions, and for 'positional popcount' big data analysis, the reduction is from over 500 instructions to 10-14 instructions.