Customers utilizing Ambarella's CV3 SoCs now have the ability to run Lauterbach's TRACE32® PowerView debug and trace software through the chips' USB 3 interface using the CSWP protocol, a standardized transport protocol that is independent of the physical link. By integrating Arms CoreSight SoC-600 IP, the SoCs can take advantage of access standards to debug memory space and an enhanced embedded trace router (ETR) that supports high-bandwidth streaming trace mode, enabling the offloading of trace data across functional interfaces.
Lauterbach's TRACE32® empowers developers to debug and trace all cores via a USB 3 interface and CSWP. With synchronization of both break-points and run-time control, developers have complete control over the entire system. The communication between the CV3 SoC and Lauterbach's PowerView software is managed by an Arm® Cortex™-M3 CPU integrated on the chip, which operates the USB stack and the CSWP server.
“As a technology leader in development tools for embedded systems, it was a natural progression for us to support CSWP debugging from the outset,” stated Norbert Weiss, Managing Director of Lauterbach GmbH. “Ambarella's CV3 SoC family possesses all the necessary chip-side prerequisites to enable customers to leverage our cutting-edge debug and trace features without limitations.”
Ambarella's ASIL D-compliant CV3 domain controller system on chip (SoC) delivers industry-leading AI performance per watt for NN computation, accommodating up to 16 Arm® Cortex®-A78AE CPUs and an automotive GPU within a single SoC. Manufactured using advanced 5 nm process technology, the CV3 serves as an ideal platform for implementing autonomous driving for vehicles ranging from L2+ to L4, single- and multi-camera ADAS, DMS, and in-cabin systems, as well as single- and multi-channel electronic mirrors with BSD, and intelligent parking assistance systems.
For more information on debugging via USB with Lauterbach's TRACE32®, visit Lauterbach's website.