OpenLane 2: Boosting Custom Open Source Chip Design

Efabless has recently unveiled the much-anticipated version 2 of the OpenLane open-source electronic design automation tools, marking a significant milestone in the field. This latest release addresses a key barrier to adoption by allowing the seamless integration of proprietary tools, opening up new possibilities for chip designers and tool developers.

With OpenLane 2, eFabless has gone back to the drawing board, redesigning the EDA infrastructure from the ground up. This overhaul enables chip designers to craft custom flows that were previously out of reach, including highly specialized steps that can now be seamlessly integrated into the design process.

OpenLane, a Python-based infrastructure tailored for implementing Application-Specific Integrated Circuits (ASICs), has been a game-changer since its inception in 2020. By amalgamating a suite of development tools such as Yosys, OpenROAD, Magic, and KLayout, OpenLane simplifies the intricate processes of silicon design into manageable steps, making it the go-to development backbone for a myriad of projects.

One of the standout features of OpenLane 2 is the introduction of a robust Python-based infrastructure that empowers users to construct fully customizable flows. This flexibility allows for the incorporation of both existing and novel steps using a mix of proprietary and open-source tools, catering to the diverse needs of chip designers and developers.

The enhanced infrastructure of OpenLane 2 supports the creation of multiple customizable flows, whether it involves integrating custom steps or leveraging advanced options for flow control. Users can now benefit from complete configuration validation, improved failure handling mechanisms, and the ability to resume flows from specific stages, all of which contribute to heightened productivity and reduced time to implementation.

OpenLane 2 ushers in a new era of customization, enabling users to write their own steps in Python, design complex flows with decision-making capabilities, and even experiment within Python Notebooks. This level of flexibility and control was previously unheard of, underscoring the commitment of Efabless to innovation and collaboration in the open-source silicon domain.