Tesla’s Dojo Training Tile in Production at TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) recently unveiled what they described as "the world's first system-on-wafer in production for next-generation data centers." This groundbreaking technology, known as the Dojo processor, is a significant leap forward in the realm of supercomputing.

The Dojo processor, also referred to as the Dojo training tile by Tesla, consists of a 5 by 5 array of D1 AI processors arranged on a carrier wafer. These processors are interconnected using TSMC's integrated fan-out (InFO) technology, resulting in the creation of a system-on-wafer (SoW) configuration.

Designed by Tesla, Dojo is a supercomputer specifically engineered to execute machine learning models that support the Full Self-Driving (FSD) advanced driver-assistance system. The Tesla D1 processor, with approximately 50 billion transistors manufactured using TSMC's 7nm process, delivers an impressive 362 Tflops of computational power per unit. While the incorporation of multiple D1 tiles within a supercomputer enhances performance, challenges related to power consumption and heat dissipation have been reported.

The initial deployment of Dojo supercomputer cabinets commenced in Palo Alto, California, with Tesla also establishing a Dojo data center at its headquarters in Austin, Texas. Furthermore, Tesla announced a substantial investment of US$500 million to construct a supercomputer cluster in Buffalo, New York, underscoring the company's commitment to advancing computational capabilities.

During a recent symposium, TSMC revealed its plans to introduce more sophisticated wafer-scale packaging by 2027. This innovative approach would enable the integration of up to 40 reticle-sized chips along with up to 60 high-bandwidth memory chips on a single wafer, further pushing the boundaries of semiconductor technology.